From: Peter Zijlstra <peterz@infradead.org>
To: Zhang Rui <rui.zhang@intel.com>
Cc: mingo@redhat.com, acme@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, jolsa@redhat.com,
namhyung@kernel.org, linux-kernel@vger.kernel.org,
x86@kernel.org, kan.liang@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
Date: Fri, 15 Jan 2021 21:03:24 +0100 [thread overview]
Message-ID: <YAH1DPNLltqN4zFR@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20210115092208.20866-2-rui.zhang@intel.com>
On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the
> energy counter, and the higher 32bits are reserved.
>
> Add the MSR mask for these MSRs to fix a problem that the RAPL PMU events
> are added erroneously when higher 32bits contain non-zero value.
Why would these high bits be non-zero?
next prev parent reply other threads:[~2021-01-15 20:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-15 9:22 [PATCH 1/3] perf/x86/rapl: Add msr mask support Zhang Rui
2021-01-15 9:22 ` [PATCH 2/3] perf/x86/rapl: Fix energy counter detection Zhang Rui
2021-01-15 20:03 ` Peter Zijlstra [this message]
2021-01-16 8:19 ` Zhang, Rui
2021-01-16 12:48 ` Peter Zijlstra
2021-01-17 14:44 ` Zhang, Rui
2021-02-03 14:21 ` Peter Zijlstra
2021-01-15 9:22 ` [PATCH 3/3] perf/x86/rapl: Fix psys-energy event on Intel SPR platform Zhang Rui
2021-01-16 12:50 ` Peter Zijlstra
2021-01-17 14:33 ` Zhang, Rui
2021-01-25 6:11 ` Zhang, Rui
2021-02-03 14:17 ` Zhang, Rui
2021-02-03 14:47 ` Peter Zijlstra
2021-02-04 16:04 ` Zhang Rui
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