Re: [PATCH v6 04/15] phy: tegra: xusb: tegra210: Do not reset UPHY PLL

JC Kuo
2021-01-20T02:03:34Z

On 1/19/21 9:52 PM, Thierry Reding wrote:
> On Tue, Jan 19, 2021 at 04:55:35PM +0800, JC Kuo wrote:
>> Once UPHY PLL hardware power sequencer is enabled, do not assert
>> reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
>> This commit removes reset_control_assert(pcie->rst) and
>> reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.
>>
>> Signed-off-by: JC Kuo <jckuo@nvidia.com>
>> ---
>> v6:
>> no change
>> v5:
>> no change
>> v4:
>> no change
>> v3:
>> new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210"
>>
>> drivers/phy/tegra/xusb-tegra210.c | 2 --
>> 1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
>> index 4dc9286ec1b8..9bfecdfecf35 100644
>> --- a/drivers/phy/tegra/xusb-tegra210.c
>> +++ b/drivers/phy/tegra/xusb-tegra210.c
>> @@ -502,7 +502,6 @@ static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
>> if (--pcie->enable > 0)
>> return;
>>
>> - reset_control_assert(pcie->rst);
>> clk_disable_unprepare(pcie->pll);
>> }
>>
>> @@ -739,7 +738,6 @@ static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
>> if (--sata->enable > 0)
>> return;
>>
>> - reset_control_assert(sata->rst);
>> clk_disable_unprepare(sata->pll);
>> }
>
> Isn't this going to break things between here and patch 5 where the
> hardware sequencer is enabled? If so, it might be better to move this
> into patch 5 so that things stay functional and bisectible.
Hi Thierry,
Yes, I will move it into patch 5.

Thanks,
JC

>
> Thierry
>