Re: [PATCH v6 12/12] x86/traps: Fix up invalid PASID

Fenghua Yu
2020-08-01T00:42:56Z

Hi, Andy,

On Fri, Jul 31, 2020 at 04:34:11PM -0700, Andy Lutomirski wrote:
> On Mon, Jul 13, 2020 at 4:48 PM Fenghua Yu <fenghua.yu@intel.com> wrote:
> >
> > A #GP fault is generated when ENQCMD instruction is executed without
> > a valid PASID value programmed in the current thread's PASID MSR. The
> > #GP fault handler will initialize the MSR if a PASID has been allocated
> > for this process.
> >
> > Decoding the user instruction is ugly and sets a bad architecture
> > precedent. It may not function if the faulting instruction is modified
> > after #GP.
> >
> > Thomas suggested to provide a reason for the #GP caused by executing ENQCMD
> > without a valid PASID value programmed. #GP error codes are 16 bits and all
> > 16 bits are taken. Refer to SDM Vol 3, Chapter 16.13 for details. The other
> > choice was to reflect the error code in an MSR. ENQCMD can also cause #GP
> > when loading from the source operand, so its not fully comprehending all
> > the reasons. Rather than special case the ENQCMD, in future Intel may
> > choose a different fault mechanism for such cases if recovery is needed on
> > #GP.
>
> Decoding the user instruction is ugly and sets a bad architecture
> precedent, but we already do it in #GP for UMIP. So I'm unconvinced.

Maybe just remove the "Decoding the user instruction ... bad architecture
precedent" sentence? The sentence is vague.

As described in the following "It may not function ..." sentence, the real
issue of parsing the instruction is the instruction may be modified by
another processor before it's parsed in the #GP handler.

If just keep the "It may not function ..." sentence, is that good enough to
explain why we don't parse the faulting instruction?

>
> Memo to Intel, though: you REALLY need to start thinking about what
> the heck an OS is supposed to do with all these new faults you're
> coming up with. The new #NM for TILE is utterly nonsensical. Sure,
> it works for an OS that does not use CR0.TS and as long as no one
> tries to extend the same mechanism for some new optional piece of
> state, but as soon as Intel tries to use the same mechanism for
> anything else, it falls apart.
>
> Please do better.

Internally we did discuss the error code in #GP for PASID with HW architects.
But due to some uarch reason, it's not simple to report the error code for
PASID:( Please see previous discussion on the error code for PASID:
https://lore.kernel.org/lkml/20200427224646.GA103955@otc-nc-03/

It's painful for our SW guys to check exception reasons if hardware
doesn't explicitly tell us.

Hopefully the heuristics (fixup the PASID MSR if the process already has
a valid PASID but the MSR doesn't have one yet) in this patch is acceptable.

>
> > +
> > +/*
> > + * Write the current task's PASID MSR/state. This is called only when PASID
> > + * is enabled.
> > + */
> > +static void fpu__pasid_write(u32 pasid)
> > +{
> > + u64 msr_val = pasid | MSR_IA32_PASID_VALID;
> > +
> > + fpregs_lock();
> > +
> > + /*
> > + * If the MSR is active and owned by the current task's FPU, it can
> > + * be directly written.
> > + *
> > + * Otherwise, write the fpstate.
> > + */
> > + if (!test_thread_flag(TIF_NEED_FPU_LOAD)) {
> > + wrmsrl(MSR_IA32_PASID, msr_val);
> > + } else {
> > + struct ia32_pasid_state *ppasid_state;
> > +
> > + ppasid_state = get_xsave_addr(&current->thread.fpu.state.xsave,
> > + XFEATURE_PASID);
> > + /*
> > + * ppasid_state shouldn't be NULL because XFEATURE_PASID
> > + * is enabled.
> > + */
> > + WARN_ON_ONCE(!ppasid_state);
> > + ppasid_state->pasid = msr_val;
>
> WARN instead of BUG is nice, but you'll immediate oops if this fails.
> How about:
>
> if (!WARN_ON_ONCE(!ppasid_state))
> ppasid_state->pasid = msr_val;

OK. I will fix this issue.

Thank you very much for your review!

-Fenghua