From: Mike Rapoport <rppt@linux.ibm.com>
To: David Hildenbrand <david@redhat.com>
Cc: "Liang, Liang (Leo)" <Liang.Liang@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
amd-gfx list <amd-gfx@lists.freedesktop.org>,
Andrew Morton <akpm@linux-foundation.org>,
"Huang, Ray" <Ray.Huang@amd.com>,
"Koenig, Christian" <Christian.Koenig@amd.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
George Kennedy <george.kennedy@oracle.com>
Subject: Re: slow boot with 7fef431be9c9 ("mm/page_alloc: place pages to tail in __free_pages_core()")
Date: Tue, 16 Mar 2021 12:30:00 +0200 [thread overview]
Message-ID: <YFCIqLmn3u1be1yo@linux.ibm.com> (raw)
In-Reply-To: <9e869214-7a3b-e86d-4832-7117f7c6090f@redhat.com>
On Tue, Mar 16, 2021 at 10:08:10AM +0100, David Hildenbrand wrote:
> On 16.03.21 09:58, Liang, Liang (Leo) wrote:
> > [AMD Public Use]
> >
> > Hi David,
> >
> > root@scbu-Chachani:~# cat /proc/mtrr
> > reg00: base=0x000000000 ( 0MB), size= 2048MB, count=1: write-back
> > reg01: base=0x0ffe00000 ( 4094MB), size= 2MB, count=1: write-protect
> > reg02: base=0x100000000 ( 4096MB), size= 16MB, count=1: write-protect
>
> ^ there it is
>
> https://wiki.osdev.org/MTRR
>
> "Reads allocate cache lines on a cache miss. All writes update main memory.
>
> Cache lines are not allocated on a write miss. Write hits invalidate the
> cache line and update main memory. "
>
> AFAIU, writes completely bypass caches and store directly to main mamory. If
> there are cache lines from a previous read, they are invalidated. So I think
> especially slow will be read(addr), write(addr), read(addr), ... which is
> what we have in the kstream benchmark.
>
>
> The question is:
>
> who sets this up without owning the memory?
> Is the memory actually special/slow or is that setting wrong?
I really doubt that 16M at 0x100000000 in a system with 8G RAM would
*physically* differ from the neighbouring memory.
> Buggy firmware/BIOS?
> Buggy device driver?
[ 0.000027] MTRR default type: uncachable
[ 0.000028] MTRR fixed ranges enabled:
[ 0.000030] 00000-9FFFF write-back
[ 0.000031] A0000-BFFFF uncachable
[ 0.000032] C0000-FFFFF write-through
[ 0.000033] MTRR variable ranges enabled:
[ 0.000034] 0 base 000000000000 mask FFFF80000000 write-back
[ 0.000036] 1 base 0000FFE00000 mask FFFFFFE00000 write-protect
[ 0.000037] 2 base 000100000000 mask FFFFFF000000 write-protect
As we have the range at 0x100000000 write-protected reported that early in
boot I'd say it's BIOS.
The question is how to reliably detect that this is a bogus setting...
[ 0.000038] 3 base 0000FFDE0000 mask FFFFFFFE0000 write-protect
[ 0.000039] 4 base 0000FF000000 mask FFFFFFF80000 write-protect
[ 0.000040] 5 disabled
[ 0.000041] 6 disabled
[ 0.000042] 7 disabled
[ 0.000042] TOM2: 0000000280000000 aka 10240M
--
Sincerely yours,
Mike.
next prev parent reply other threads:[~2021-03-16 10:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 14:41 slow boot with 7fef431be9c9 ("mm/page_alloc: place pages to tail in __free_pages_core()") Deucher, Alexander
2021-03-11 15:02 ` David Hildenbrand
2021-03-12 14:06 ` Deucher, Alexander
2021-03-12 14:12 ` David Hildenbrand
2021-03-12 15:39 ` Deucher, Alexander
2021-03-12 15:48 ` David Hildenbrand
2021-03-12 16:15 ` Deucher, Alexander
2021-03-12 16:19 ` Liang, Liang (Leo)
2021-03-12 16:46 ` David Hildenbrand
2021-03-13 4:04 ` Liang, Liang (Leo)
2021-03-13 9:05 ` David Hildenbrand
2021-03-13 13:48 ` Mike Rapoport
2021-03-15 13:04 ` David Hildenbrand
2021-03-16 0:36 ` Liang, Liang (Leo)
2021-03-16 6:50 ` Mike Rapoport
2021-03-16 8:00 ` Liang, Liang (Leo)
2021-03-16 8:37 ` David Hildenbrand
2021-03-16 8:43 ` Liang, Liang (Leo)
2021-03-16 8:54 ` David Hildenbrand
2021-03-16 8:58 ` Liang, Liang (Leo)
2021-03-16 9:08 ` David Hildenbrand
2021-03-16 10:30 ` Mike Rapoport [this message]
2021-03-16 11:02 ` Liang, Liang (Leo)
2021-03-16 11:10 ` David Hildenbrand
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