Re: [PATCH v1 6/7] mfd: lpc_ich: Add support for pinctrl in non-ACPI system

Andy Shevchenko
2021-04-12T17:41:49Z

On Mon, Apr 12, 2021 at 07:27:14PM +0200, Henning Schild wrote:
> Am Mon, 12 Apr 2021 19:51:42 +0300
> schrieb Andy Shevchenko <andriy.shevchenko@linux.intel.com>:
> > On Mon, Apr 12, 2021 at 06:01:06PM +0200, Henning Schild wrote:
> > > Am Mon, 8 Mar 2021 14:20:19 +0200
> > > schrieb Andy Shevchenko <andriy.shevchenko@linux.intel.com>:

...

> > > > +#define APL_GPIO_NORTH_OFFSET 0xc50000
> > > > +#define APL_GPIO_NORTH_SIZE 0x76c
> > >
> > > drivers/pinctrl/intel/pinctrl-broxton.c:653
> > > BXT_COMMUNITY(0, 77),
> > >
> > > > +#define APL_GPIO_WEST_OFFSET 0xc70000
> > > > +#define APL_GPIO_WEST_SIZE 0x674
> > >
> > > All these sizes correlate with 4 magic numbers from pinctrl-broxton.
> > >
> > > SIZE - 0x500 (pad_base?) - 4 (no clue) / 8
> > >
> > > It might be worth basing both numbers on a define and giving the
> > > magic numbers some names.
> >
> > I didn't get this, sorry. The numbers above just precise sizes of the
> > resources. Actually they all one page anyway, so, I can drop magic of
> > SIZEs and leave only offsets.
>
> That precise size is also in the broxton driver, i think. Say we did
> have
>
> #define BXT_NORTH_COUNT 77
> #define PAD_BASE 0x500
>
> in some central place
>
> then we could use
>
> size = 0x500 + 8 * BXT_NORTH_COUNT + 4 (no clue what that is)
>
> the same pattern would work for all those sizes and their
> BXT_COMMUNITY(0, XX) counterparts
>
> So the real size seems to be a function of the magic numbers in
> BXT_COMMUNITY(0, XX)
>
> Or simply take one page as you say.

No, not this way. We are really trying hard *not* to put *that* magic into
the code. Just FYI that SIZEs I have calculated myself, but these SIZEs
are *not* the same as the ones used in pinctrl-broxton *semantically*.

One if for resource provider, one is for consumer. They are simply different
in this sense.

> > > But all this seems like duplication of pinctrl-broxton, maybe the
> > > pinctrl driver should unhide the p2sb ...
> >
> > Definitely should not. It's not a business of the pin control driver
> > to know how it has to be instantiated (or from what data). These
> > offsets belong to the platform description and since firmware hides
> > the device without given an appropriate ACPI device node, we have
> > only one choice (assuming firmware is carved in stone) -- board files.
> >
> > P2SB on the other hand is a slice of many (independent) devices.
> > There is no "proper" place to unhide it except some core part of x86
> > / PCI.
>
> Got it, still the fact that there are 4 regions/communities is also part
> of the broxton driver so there is duplication.

See above. I guess here is a misunderstanding behind meaning of the (same)
numbers in different parts. Technically we may unify them, but it will be
a layering violation.

--
With Best Regards,
Andy Shevchenko