From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E37C07E94 for ; Fri, 4 Jun 2021 07:43:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0177613BF for ; Fri, 4 Jun 2021 07:43:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230192AbhFDHpk (ORCPT ); Fri, 4 Jun 2021 03:45:40 -0400 Received: from muru.com ([72.249.23.125]:36152 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229958AbhFDHpj (ORCPT ); Fri, 4 Jun 2021 03:45:39 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id E17AE8167; Fri, 4 Jun 2021 07:43:58 +0000 (UTC) Date: Fri, 4 Jun 2021 10:43:48 +0300 From: Tony Lindgren To: Sven Peter Cc: Rob Herring , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> <1ff54382-7137-49d6-841d-318e400e956e@www.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1ff54382-7137-49d6-841d-318e400e956e@www.fastmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Sven Peter [210603 12:56]: > Another possibility this made me think of is to instead just use the clocks > property the way it's usually used and simply refer to the controller itself, e.g. > > #define APPLE_CLK_UART0 0x270 > #define APPLE_CLK_UART_P 0x220 > #define APPLE_CLK_SIO 0x1c0 > > pmgr0: clock-controller@23b700000 { > compatible = "apple,t8103-gate-clock"; > #clock-cells = <1>; > reg = <0x2 0x3b700000 0x0 0x4000>; > clock-indices = , , ; > clock-output-names = "clock-sio", "clock-uart-", "clock-uart0"; > clocks = <&some_dummy_root_clock>, <&pmgr0 APPLE_CLK_SIO>, > <&pmgr0 APPLE_CLK_UART_P>; > }; How about the following where you set up the gate clocks as separate child nodes: pmgr0: clock-controller@23b700000 { compatible = "apple,foo-clock-controller"; #clock-cells = <1>; reg = <0x2 0x3b700000 0x0 0x4000>; clk_uart0: clock@270 { compatible = "apple,t8103-gate-clock"; #clock-cells = <0>; assigned-clock-parents = <&pmgr0 APPLE_CLK_SIO>, <&pmgr0 APPLE_CLK_UART_P>; // ... }; }; Keep the clock controller still addressable by offset from base as discussed, and additionally have the driver parse and set up the child node clocks. Then I think the consumer driver can just do: serial0: serial@235200000 { // ... clocks = <&clk_uart0>, <&clk24>; clock-names = "uart", "clk_uart_baud0"; // ... }; Regards, Tony