Re: [PATCH] x86/perf: Fixed obtaining address error about performance monitor MSR on old Inel CPU.

[Sean Christopherson <seanjc@google.com>]

On Fri, Jun 04, 2021, Cody Yao-oc wrote:
> From: CodyYao-oc <CodyYao-oc@zhaoxin.com>
> 
> Fix "obtain wrong msr address" bug in function nmi_perfctr_msr_to_bit
> and nmi_eventsel_msr_to_bit. In X86_VENDOR_INTEL switch branch, if all
> of the check conditions are not met, code flow will slip to
> X86_VENDOR_ZHAOXIN branch which may lead to incorrect information.
> 
> Therefore, "fallthrough" should be changed to "break" to avoid it.

This should explicitly state that using fallthrough instead of break was
completely unintentional, assuming that's indeed the case.

Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.")

> Signed-off-by: CodyYao-oc <CodyYao-oc@zhaoxin.com>
> ---
>  arch/x86/kernel/cpu/perfctr-watchdog.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
> index 3ef5868ac588..7aecb2fc3186 100644
> --- a/arch/x86/kernel/cpu/perfctr-watchdog.c
> +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
> @@ -63,7 +63,7 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
>  		case 15:
>  			return msr - MSR_P4_BPU_PERFCTR0;
>  		}
> -		fallthrough;
> +		break;
>  	case X86_VENDOR_ZHAOXIN:
>  	case X86_VENDOR_CENTAUR:
>  		return msr - MSR_ARCH_PERFMON_PERFCTR0;
> @@ -96,7 +96,7 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
>  		case 15:
>  			return msr - MSR_P4_BSU_ESCR0;
>  		}
> -		fallthrough;
> +		break;
>  	case X86_VENDOR_ZHAOXIN:
>  	case X86_VENDOR_CENTAUR:
>  		return msr - MSR_ARCH_PERFMON_EVENTSEL0;
> -- 
> 2.17.1
>