Re: [PATCH 2/8] dt-bindings: pinctrl: qcom,pmic-gpio: Add compatible for SA8155p-adp

Bjorn Andersson
2021-06-14T16:09:25Z

On Mon 14 Jun 03:13 CDT 2021, Bhupesh Sharma wrote:

> Hi Bjorn,
>
> On Fri, 11 Jun 2021 at 08:21, Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
> >
> > On Mon 07 Jun 06:38 CDT 2021, Bhupesh Sharma wrote:
> >
> > > Add pmic-gpio compatible strings for pmm8155au_1 and pmm8155au_2 pmics
> > > found on SA8155p-adp board.
> > >
> > > Cc: Linus Walleij <linus.walleij@linaro.org>
> > > Cc: Liam Girdwood <lgirdwood@gmail.com>
> > > Cc: Mark Brown <broonie@kernel.org>
> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > Cc: Vinod Koul <vkoul@kernel.org>
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Andy Gross <agross@kernel.org>
> > > Cc: devicetree@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: linux-gpio@vger.kernel.org
> > > Cc: bhupesh.linux@gmail.com
> > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > > ---
> > > Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
> > > index f6a9760558a6..ee4721f1c477 100644
> > > --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
> > > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
> > > @@ -27,6 +27,8 @@ PMIC's from Qualcomm.
> > > "qcom,pm660l-gpio"
> > > "qcom,pm8150-gpio"
> > > "qcom,pm8150b-gpio"
> > > + "qcom,pmm8155au-1-gpio"
> > > + "qcom,pmm8155au-2-gpio"
> >
> > As with the regulator this seems to be a single component.
> >
> > > "qcom,pm8350-gpio"
> > > "qcom,pm8350b-gpio"
> > > "qcom,pm8350c-gpio"
> > > @@ -116,6 +118,9 @@ to specify in a pin configuration subnode:
> > > and gpio8)
> > > gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
> > > gpio1-gpio12 for pm8150l (hole on gpio7)
> > > + gpio1-gpio10 for pmm8155au-1 (holes on gpio2, gpio5, gpio7
> > > + and gpio8)
> > > + gpio1-gpio10 for pmm8155au-2 (holes on gpio2, gpio5, gpio7)
> >
> > In the schematics all 10 pins are wired on both of these PMICs, so I
> > don't think there are holes. Please omit the comment.
>
> But if we look at the downstream dts (see [1]), we clearly have holes
> on gpio 2, 5 and 7 on PMM8155AU_2 whereas if we see [2], we can see
> PMM8155AU_1 has holes on gpio 2, 5, 7 and 8.
>
> As I understand, the schematics mention some optional configurations
> as well which might not be available depending on the default board
> configuration.
>
> [1]. https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sa8155-pmic-overlay.dtsi?h=LV.AU.0.1.0.r1-15900-gen3meta.0#n92
> [2]. https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sa8155-pmic-overlay.dtsi?h=LV.AU.0.1.0.r1-15900-gen3meta.0#n36
>

Perhaps these "holes" means that they are reserved for use by one of the
other subsystems in the SoC - similar to how we have
gpio-reserved-ranges in the TLMM. Because according to the PMS8155AU
documentation and the schematics, there's no physical holes there.

As such, the binding and driver should not describe these "holes". If
they aren't used by Linux, then the DT won't reference them - and if
there's reasons for prohibiting Linux from touching the registers we
should use gpio-reserved-ranges, as this will depend on firmware
configuration.

Regards,
Bjorn

> Regards,
> Bhupesh
>
> >
> > > gpio1-gpio10 for pm8350
> > > gpio1-gpio8 for pm8350b
> > > gpio1-gpio9 for pm8350c
> > > --
> > > 2.31.1
> > >