RE: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend")

Quan, Evan
2021-10-09T01:20:45Z

[AMD Official Use Only]

Maybe the change below can address your issue.
https://lists.freedesktop.org/archives/amd-gfx/2021-September/069006.html

BR
Evan
> -----Original Message-----
> From: Borislav Petkov <bp@alien8.de>
> Sent: Friday, October 8, 2021 11:36 PM
> To: Alex Deucher <alexdeucher@gmail.com>
> Cc: Quan, Evan <Evan.Quan@amd.com>; amd-gfx list <amd-
> gfx@lists.freedesktop.org>; LKML <linux-kernel@vger.kernel.org>; Deucher,
> Alexander <Alexander.Deucher@amd.com>; Pan, Xinhui
> <Xinhui.Pan@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>
> Subject: Re: bf756fb833cb ("drm/amdgpu: add missing cleanups for Polaris12
> UVD/VCE on suspend")
>
> On Fri, Oct 08, 2021 at 11:12:35AM -0400, Alex Deucher wrote:
> > Can you try swapping the order of
> > amdgpu_device_ip_set_powergating_state() and
> > amdgpu_device_ip_set_clockgating_state() in the patch?
>
> Nope, the diff below didn't change things.
>
> Should I comment them out one by one and see whether the clockgating or
> the powergating causes it?
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index bc571833632e..99e3d697cc24 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -561,10 +561,10 @@ static int uvd_v6_0_hw_fini(void *handle)
> } else {
> amdgpu_asic_set_uvd_clocks(adev, 0, 0);
> /* shutdown the UVD block */
> - amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_UVD,
> + AMD_PG_STATE_GATE);
> }
>
> if (RREG32(mmUVD_STATUS) != 0)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9de66893ccd6..a36612357d0f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -507,10 +507,10 @@ static int vce_v3_0_hw_fini(void *handle)
> amdgpu_dpm_enable_vce(adev, false);
> } else {
> amdgpu_asic_set_vce_clocks(adev, 0, 0);
> - amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> - AMD_PG_STATE_GATE);
> amdgpu_device_ip_set_clockgating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_CG_STATE_GATE);
> + amdgpu_device_ip_set_powergating_state(adev,
> AMD_IP_BLOCK_TYPE_VCE,
> + AMD_PG_STATE_GATE);
> }
>
> r = vce_v3_0_wait_for_idle(handle);
>
> --
> Regards/Gruss,
> Boris.
>
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