From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B628DC433EF for ; Mon, 18 Oct 2021 06:56:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 995E66108E for ; Mon, 18 Oct 2021 06:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbhJRG6Q (ORCPT ); Mon, 18 Oct 2021 02:58:16 -0400 Received: from mga03.intel.com ([134.134.136.65]:25893 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229533AbhJRG6O (ORCPT ); Mon, 18 Oct 2021 02:58:14 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10140"; a="228131545" X-IronPort-AV: E=Sophos;i="5.85,381,1624345200"; d="scan'208";a="228131545" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Oct 2021 23:56:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,381,1624345200"; d="scan'208";a="489304579" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 17 Oct 2021 23:56:00 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 18 Oct 2021 09:55:59 +0300 Date: Mon, 18 Oct 2021 09:55:59 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Borislav Petkov Cc: Ser Olmy , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits") Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 15, 2021 at 01:04:28PM +0200, Borislav Petkov wrote: > Ok, here it is. Thanks. I got distracted by other shiny objects anyway, so wouldn't even have gotten to cooking up a proper patch until now. > > Ser, I'd appreciate you running it too, to make sure your box is still > ok. > > Thx. > > --- > From: Borislav Petkov > Date: Fri, 15 Oct 2021 12:46:25 +0200 > Subject: [PATCH] x86/fpu: Mask out the invalid MXCSR bits properly > MIME-Version: 1.0 > Content-Type: text/plain; charset=UTF-8 > Content-Transfer-Encoding: 8bit > > This is a fix for the fix (yeah, /facepalm). > > The correct mask to use is not the negation of the MXCSR_MASK but the > actual mask which contains the supported bits in the MXCSR register. > > Reported and debugged by Ville Syrjälä > > Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits") > Signed-off-by: Borislav Petkov > Cc: > Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@intel.com > --- > arch/x86/kernel/fpu/signal.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c > index fa17a27390ab..831b25c5e705 100644 > --- a/arch/x86/kernel/fpu/signal.c > +++ b/arch/x86/kernel/fpu/signal.c > @@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, > return -EINVAL; > } else { > /* Mask invalid bits out for historical reasons (broken hardware). */ > - fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; > + fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; > } > > /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ > -- > 2.29.2 > > -- > Regards/Gruss, > Boris. > > https://people.kernel.org/tglx/notes-about-netiquette -- Ville Syrjälä Intel