From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FD6FC4332F for ; Mon, 18 Oct 2021 16:43:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 616BF60F12 for ; Mon, 18 Oct 2021 16:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233692AbhJRQpl (ORCPT ); Mon, 18 Oct 2021 12:45:41 -0400 Received: from mail-oi1-f177.google.com ([209.85.167.177]:35451 "EHLO mail-oi1-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231793AbhJRQpk (ORCPT ); Mon, 18 Oct 2021 12:45:40 -0400 Received: by mail-oi1-f177.google.com with SMTP id r6so628455oiw.2; Mon, 18 Oct 2021 09:43:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=/vsPv2SD1Rt8WbOkNW13ZNWlyAjKc3bg4K4BxMrdTKc=; b=Pa6GomVbVXYYe/9ExmVV6kjIEgfq6uTGu8OoluinqdpUSOiTZd7nMFcCHluXIbqmw4 I5DpeX3U/Hcg8fg8zzx1e6bfYfHVq99iQ81E8LhiOgidhHSY4ha32kTCz7H91erY0qE7 uDYZMpjGrMBGdeWquNXi+BSv3ibalgE1WQGlOeOVwmIpq2An5FlypjmQdse26FIF86Yb UzBI+lAU1YFaI1OU7bXE+hKwSPzps/qLc3cXONFyTNalf3XegM+AqzNGwOtJf9XSDnyN MchZC3ppEXyZ2yaaQVusE/3b85XoSUPcebpE8KIw3PZvZAydLhE04NUy5RoJHXeNT9ff kowg== X-Gm-Message-State: AOAM530uSZt1A8JjgzJW0dcWQTK14lrQTnc13P/SPvDAyydjuieXmwfS hQdMOICgtICvx7+J7JBmFQ== X-Google-Smtp-Source: ABdhPJxOfGc66L0/rXjSFdldE/BLsaDwndHWOMX5LeqJpkR4KftoMRAgJrb4lXRb41d95MOC+xLB+g== X-Received: by 2002:a05:6808:7c8:: with SMTP id f8mr638949oij.146.1634575408315; Mon, 18 Oct 2021 09:43:28 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id ay42sm3156043oib.22.2021.10.18.09.43.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Oct 2021 09:43:27 -0700 (PDT) Received: (nullmailer pid 2532419 invoked by uid 1000); Mon, 18 Oct 2021 16:43:26 -0000 Date: Mon, 18 Oct 2021 11:43:26 -0500 From: Rob Herring To: Sean Anderson Cc: linux-arm-kernel@lists.infradead.org, Thierry Reding , linux-kernel@vger.kernel.org, Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Alvaro Gamez , devicetree@vger.kernel.org, Lee Jones , michal.simek@xilinx.com, linux-pwm@vger.kernel.org Subject: Re: [PATCH v8 2/3] dt-bindings: pwm: Add Xilinx AXI Timer Message-ID: References: <20211015190025.409426-1-sean.anderson@seco.com> <20211015190025.409426-2-sean.anderson@seco.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211015190025.409426-2-sean.anderson@seco.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 15 Oct 2021 15:00:24 -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > "soft" block, so it has some parameters which would not be configurable in > most hardware. This binding is usually automatically generated by Xilinx's > tools, so the names and values of some properties should be kept as they > are, if possible. In addition, this binding is already in the kernel at > arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. > > The existing driver uses the clock-frequency property, or alternatively the > /cpus/timebase-frequency property as its frequency input. Because these > properties are deprecated, they have not been included with this schema. > All new bindings should use the clocks/clock-names properties to specify > the parent clock. > > Because we need to init timer devices so early in boot, we determine if we > should use the PWM driver or the clocksource/clockevent driver by the > presence/absence, respectively, of #pwm-cells. Because both counters are > used by the PWM, there is no need for a separate property specifying which > counters are to be used for the PWM. > > Signed-off-by: Sean Anderson > --- > > Changes in v8: > - Set additionalProperties: false > > Changes in v7: > - Add #pwm-cells to properties > - Document why additionalProperties is true > > Changes in v6: > - Enumerate possible counter widths > - Fix incorrect schema id > > Changes in v5: > - Add example for timer binding > - Fix indentation lint > - Move schema into the timer directory > - Remove xlnx,axi-timer-2.0 compatible string > - Update commit message to reflect revisions > > Changes in v4: > - Make some properties optional for clocksource drivers > - Predicate PWM driver on the presence of #pwm-cells > - Remove references to generate polarity so this can get merged > > Changes in v3: > - Add an example with non-deprecated properties only. > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Mark all boolean-as-int properties as deprecated > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/timer/xlnx,xps-timer.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > Reviewed-by: Rob Herring