From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1D19C433F5 for ; Fri, 8 Oct 2021 09:07:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 889DE6103C for ; Fri, 8 Oct 2021 09:07:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbhJHJJY (ORCPT ); Fri, 8 Oct 2021 05:09:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:34080 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229853AbhJHJJW (ORCPT ); Fri, 8 Oct 2021 05:09:22 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3A7B860F6E; Fri, 8 Oct 2021 09:07:25 +0000 (UTC) Date: Fri, 8 Oct 2021 10:07:22 +0100 From: Catalin Marinas To: Zhaoyang Huang Cc: Will Deacon , Mark Rutland , Suzuki K Poulose , Ionela Voinescu , Quentin Perret , Vladimir Murzin , linux-arm-kernel@lists.infradead.org, Zhaoyang Huang , LKML , Ke Wang , ping.zhou1@unisoc.com Subject: Re: [RFC PATCH] arch: ARM64: add isb before enable pan Message-ID: References: <1633673269-15048-1-git-send-email-huangzhaoyang@gmail.com> <20211008080113.GA441@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 08, 2021 at 04:55:05PM +0800, Zhaoyang Huang wrote: > On Fri, Oct 8, 2021 at 4:45 PM Catalin Marinas wrote: > > On Fri, Oct 08, 2021 at 04:34:12PM +0800, Zhaoyang Huang wrote: > > > On Fri, Oct 8, 2021 at 4:01 PM Will Deacon wrote: > > > > On Fri, Oct 08, 2021 at 02:07:49PM +0800, Huangzhaoyang wrote: > > > > > From: Zhaoyang Huang > > > > > > > > > > set_pstate_pan failure is observed in an ARM64 system occasionaly on a reboot > > > > > test, which can be work around by a msleep on the sw context. We assume > > > > > suspicious on disorder of previous instr of disabling SW_PAN and add an isb here. > > > > > > > > > > PS: > > > > > The bootup test failed with a invalid TTBR1_EL1 that equals 0x34000000, which is > > > > > alike racing between on chip PAN and SW_PAN. > > > > > > > > Sorry, but I'm struggling to understand the problem here. Please could you > > > > explain it in more detail? > > > > > > > > - Why does a TTBR1_EL1 value of `0x34000000` indicate a race? > > > > - Can you explain the race that you think might be occurring? > > > > - Why does an ISB prevent the race? > > > Please find panic logs[1], related codes[2], sample of debug patch[3] > > > below. TTBR1_EL1 equals 0x34000000 when panic and can NOT be captured > > > by the debug patch during retest (all entrances that msr ttbr1_el1 are > > > under watch) which should work. Adding ISB here to prevent race on > > > TTBR1 from previous access of sysregs which can affect the msr > > > result(the test is still ongoing). Could the race be > > > ARM64_HAS_PAN(automated by core) and SW_PAN. > > > > Can you please change the ARM64_HAS_PAN type to > > ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE? I wonder whether > > system_uses_ttbr0_pan() changes its output when all CPUs had been > > brought up and system_uses_hw_pan() returns true. > > ok, thanks. We will try. Is it a workaround for known defect? No, other than the potential kernel bug you reported. -- Catalin