From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8B8FC433F5 for ; Fri, 15 Oct 2021 18:00:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9090F6121E for ; Fri, 15 Oct 2021 18:00:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242404AbhJOSCL (ORCPT ); Fri, 15 Oct 2021 14:02:11 -0400 Received: from mail.kernel.org ([198.145.29.99]:60294 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237569AbhJOSCJ (ORCPT ); Fri, 15 Oct 2021 14:02:09 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2116361212; Fri, 15 Oct 2021 18:00:01 +0000 (UTC) Date: Fri, 15 Oct 2021 18:59:58 +0100 From: Catalin Marinas To: Xiongfeng Wang Cc: mark.rutland@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, moyufeng@huawei.com Subject: Re: [RFC PATCH v2] arm64: barrier: add macro dgh() to control memory accesses merging Message-ID: References: <20211015090511.92421-1-wangxiongfeng2@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211015090511.92421-1-wangxiongfeng2@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 15, 2021 at 05:05:11PM +0800, Xiongfeng Wang wrote: > diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h > index 451e11e5fd23..d71a7457d619 100644 > --- a/arch/arm64/include/asm/barrier.h > +++ b/arch/arm64/include/asm/barrier.h > @@ -18,6 +18,14 @@ > #define wfe() asm volatile("wfe" : : : "memory") > #define wfi() asm volatile("wfi" : : : "memory") > > +/* > + * Data Gathering Hint: > + * This instruction prohibits merging memory accesses with Normal-NC or > + * Device-GRE attributes before the hint instruction with any memory accesses > + * appearing after the hint instruction. > + */ > +#define dgh() asm volatile("hint #6" : : : "memory") On its own, this patch doesn't do anything. It's more interesting to see how it will be used and maybe come up with a common name that other architectures would share (or just implement as no-opp). I'm not sure there was any conclusion last time we discussed this. -- Catalin