From: Paul Cercueil <paul@crapouillou.net>
To: 周琰杰 <zhouyanjie@wanyeetech.com>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
hns@goldelico.com, paul@boddie.org.uk, andy.shevchenko@gmail.com,
dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
sernia.zhou@foxmail.com
Subject: Re: [PATCH v3 02/10] pinctrl: Ingenic: Add support for read the pin configuration of X1830.
Date: Mon, 22 Mar 2021 17:58:46 +0000 [thread overview]
Message-ID: <YXTDQQ.OYIQVLSUOAPB3@crapouillou.net> (raw)
In-Reply-To: <1615975084-68203-3-git-send-email-zhouyanjie@wanyeetech.com>
Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Add X1830 support in "ingenic_pinconf_get()", so that it can read the
> configuration of X1830 SoC correctly.
>
> Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for
> X1830.")
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
>
> Notes:
> v2:
> New patch.
>
> v2->v3:
> 1.Add fixes tag.
> 2.Adjust the code, simplify the ingenic_pinconf_get() function.
>
> drivers/pinctrl/pinctrl-ingenic.c | 38
> ++++++++++++++++++++++++++++++--------
> 1 file changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-ingenic.c
> b/drivers/pinctrl/pinctrl-ingenic.c
> index 05dfa0a..1d43b98 100644
> --- a/drivers/pinctrl/pinctrl-ingenic.c
> +++ b/drivers/pinctrl/pinctrl-ingenic.c
> @@ -2109,26 +2109,48 @@ static int ingenic_pinconf_get(struct
> pinctrl_dev *pctldev,
> enum pin_config_param param = pinconf_to_config_param(*config);
> unsigned int idx = pin % PINS_PER_GPIO_CHIP;
> unsigned int offt = pin / PINS_PER_GPIO_CHIP;
> - bool pull;
> + unsigned int bias;
> + bool pull, pullup, pulldown;
>
> - if (jzpc->info->version >= ID_JZ4770)
> - pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
> - else
> - pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
> + if (jzpc->info->version >= ID_X1830) {
> + unsigned int half = PINS_PER_GPIO_CHIP / 2;
> + unsigned int idxh = pin % half * 2;
I had to look up operator precedence in C, '*' and '%' have the same
priority so this reads left-to-right.
I'd suggest adding parentheses around the '%' to make it more obvious.
With that:
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> +
> + if (idx < half)
> + regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
> + X1830_GPIO_PEL, &bias);
> + else
> + regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
> + X1830_GPIO_PEH, &bias);
> +
> + bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
> +
> + pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] &
> BIT(idx));
> + pulldown = (bias == GPIO_PULL_DOWN) &&
> (jzpc->info->pull_downs[offt] & BIT(idx));
> +
> + } else {
> + if (jzpc->info->version >= ID_JZ4770)
> + pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
> + else
> + pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
> +
> + pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
> + pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
> + }
>
> switch (param) {
> case PIN_CONFIG_BIAS_DISABLE:
> - if (pull)
> + if (pullup || pulldown)
> return -EINVAL;
> break;
>
> case PIN_CONFIG_BIAS_PULL_UP:
> - if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
> + if (!pullup)
> return -EINVAL;
> break;
>
> case PIN_CONFIG_BIAS_PULL_DOWN:
> - if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
> + if (!pulldown)
> return -EINVAL;
> break;
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-03-22 17:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 9:57 [PATCH v3 00/10] Fix bugs and add support for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-03-17 9:57 ` [PATCH v3 01/10] pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group 周琰杰 (Zhou Yanjie)
2021-03-22 17:53 ` Paul Cercueil
2021-03-25 7:37 ` Zhou Yanjie
2021-03-17 9:57 ` [PATCH v3 02/10] pinctrl: Ingenic: Add support for read the pin configuration of X1830 周琰杰 (Zhou Yanjie)
2021-03-22 17:58 ` Paul Cercueil [this message]
2021-03-25 7:38 ` Zhou Yanjie
2021-03-17 9:57 ` [PATCH v3 03/10] pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups 周琰杰 (Zhou Yanjie)
2021-03-17 9:57 ` [PATCH v3 04/10] pinctrl: Ingenic: Reformat the code 周琰杰 (Zhou Yanjie)
2021-03-17 9:57 ` [PATCH v3 05/10] dt-bindings: pinctrl: Add bindings for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-03-22 18:01 ` Paul Cercueil
2021-03-25 7:43 ` Zhou Yanjie
2021-03-26 0:18 ` Rob Herring
2021-03-17 9:58 ` [PATCH v3 06/10] pinctrl: Ingenic: Add pinctrl driver for JZ4730 周琰杰 (Zhou Yanjie)
2021-03-22 18:17 ` Paul Cercueil
2021-03-25 7:55 ` Zhou Yanjie
2021-03-17 9:58 ` [PATCH v3 07/10] pinctrl: Ingenic: Add pinctrl driver for JZ4750 周琰杰 (Zhou Yanjie)
2021-03-22 18:20 ` Paul Cercueil
2021-03-25 7:55 ` Zhou Yanjie
2021-03-17 9:58 ` [PATCH v3 08/10] pinctrl: Ingenic: Add pinctrl driver for JZ4755 周琰杰 (Zhou Yanjie)
2021-03-22 18:24 ` Paul Cercueil
2021-03-25 8:38 ` Zhou Yanjie
2021-03-27 18:30 ` Paul Cercueil
2021-03-29 9:15 ` Zhou Yanjie
2021-03-17 9:58 ` [PATCH v3 09/10] pinctrl: Ingenic: Add pinctrl driver for JZ4775 周琰杰 (Zhou Yanjie)
2021-03-22 18:25 ` Paul Cercueil
2021-03-25 8:39 ` Zhou Yanjie
2021-03-17 9:58 ` [PATCH v3 10/10] pinctrl: Ingenic: Add pinctrl driver for X2000 周琰杰 (Zhou Yanjie)
2021-03-22 18:39 ` Paul Cercueil
[not found] ` <fc1019bb-86c7-072a-b60c-3511c38858d2@wanyeetech.com>
2021-03-27 19:58 ` Paul Cercueil
2021-03-29 9:18 ` Zhou Yanjie
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