From: Rob Herring <robh@kernel.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: linux-kernel@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
David Abdurachmanov <david.abdurachmanov@sifive.com>,
devicetree@vger.kernel.org,
Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@linux.alibaba.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Jonathan Corbet <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
Nick Kossifidis <mick@ics.forth.gr>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [v4 06/11] dt-binding: pmu: Add RISC-V PMU DT bindings
Date: Tue, 26 Oct 2021 13:57:45 -0500 [thread overview]
Message-ID: <YXhPqfpXh1VZN07T@robh.at.kernel.org> (raw)
In-Reply-To: <20211025195350.242914-7-atish.patra@wdc.com>
On Mon, Oct 25, 2021 at 12:53:45PM -0700, Atish Patra wrote:
> This patch adds the DT bindings for RISC-V PMU driver. It also defines
> the interrupt related properties to allow counter overflow interrupt.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> .../devicetree/bindings/perf/riscv,pmu.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> new file mode 100644
> index 000000000000..497caad63f16
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pmu/riscv,pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V PMU
> +
> +maintainers:
> + - Atish Patra <atish.patra@wdc.com>
> +
> +description:
> + The "Sscofpmf" extension allows the RISC-V PMU counters to overflow and
> + generate a local interrupt so that event sampling can be done from user-space.
> + The above said ISA extension is an optional extension to maintain backward
> + compatibility and will be included in privilege specification v1.12 . That's
> + why the interrupt property is marked as optional. The platforms with sscofpmf
> + extension should add this property to enable event sampling.
> + The device tree node with the compatible string is mandatory for any platform
> + that wants to use pmu counter start/stop methods using SBI PMU extension.
> +
> +properties:
> + compatible:
> + enum:
> + - riscv,pmu
Only 1 version? Every implementation detail is discoverable in other
ways?
> +
> + description:
> + Should be "riscv,pmu".
Don't write free form text of what the schema says.
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4095
> +
> +additionalProperties: false
> +
> +required:
> + - None
> +optional:
No a json-schema keyword.
> + - compatible
> + - interrupts-extended
> +
> +examples:
> + - |
> + pmu {
> + compatible = "riscv,pmu";
> + interrupts-extended = <&cpu0intc 13>,
> + <&cpu1intc 13>,
> + <&cpu2intc 13>,
> + <&cpu3intc 13>;
> + };
> +...
> --
> 2.31.1
>
>
next prev parent reply other threads:[~2021-10-26 18:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 19:53 [v4 00/11] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2021-10-25 19:53 ` [v4 01/11] RISC-V: Remove the current perf implementation Atish Patra
2021-10-25 19:53 ` [v4 02/11] RISC-V: Add CSR encodings for all HPMCOUNTERS Atish Patra
2021-10-25 19:53 ` [v4 03/11] RISC-V: Add a perf core library for pmu drivers Atish Patra
2021-10-25 19:53 ` [v4 04/11] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2021-10-25 19:53 ` [v4 05/11] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2021-12-15 8:02 ` Nikita Shubin
2021-12-15 16:03 ` Atish Patra
2021-10-25 19:53 ` [v4 06/11] dt-binding: pmu: Add RISC-V PMU DT bindings Atish Patra
2021-10-26 18:03 ` Rob Herring
2021-10-26 18:57 ` Rob Herring [this message]
2021-10-28 20:17 ` Jessica Clarke
2021-10-25 19:53 ` [v4 07/11] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2021-10-25 19:53 ` [v4 08/11] RISC-V: Add interrupt support for perf Atish Patra
2021-10-25 19:53 ` [v4 09/11] Documentation: riscv: Remove the old documentation Atish Patra
2021-10-25 19:53 ` [v4 10/11] riscv: dts: fu740: Add pmu node Atish Patra
2021-10-28 20:48 ` Jessica Clarke
2021-10-28 23:37 ` Atish Patra
2021-10-29 0:07 ` Jessica Clarke
2021-10-29 6:05 ` Atish Patra
2021-10-29 12:25 ` Jessica Clarke
2021-10-25 19:53 ` [v4 11/11] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2021-12-14 1:51 ` [v4 00/11] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Palmer Dabbelt
2021-12-14 3:16 ` Atish Patra
2021-12-14 18:09 ` Will Deacon
2021-12-14 9:14 ` Nikita Shubin
2021-12-14 18:29 ` Atish Patra
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