Re: [PATCH v6 2/9] dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators

Rob Herring
2021-11-02T15:18:23Z

On Fri, Oct 29, 2021 at 04:03:10PM -0400, Jim Quinlan wrote:
> Similar to the regulator bindings found in "rockchip-pcie-host.txt", this
> allows optional regulators to be attached and controlled by the PCIe RC
> driver. That being said, this driver searches in the DT subnode (the EP
> node, eg pci-ep@0,0) for the regulator property.
>
> The use of a regulator property in the pcie EP subnode such as
> "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml
> file at
>
> https://github.com/devicetree-org/dt-schema/pull/63
>
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
> .../bindings/pci/brcm,stb-pcie.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 508e5dce1282..d90d867deb5c 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -62,6 +62,10 @@ properties:
>
> aspm-no-l0s: true
>
> + vpcie12v-supply: true
> + vpcie3v3-supply: true
> + vpcie3v3aux-supply: true
> +

You've put these in the host bridge node and in *any* bridge node for
pci-bus.yaml, but that's not where you have them in the example.

The question is where is the right place. Normally, I'd say that's in
the node consuming or connected to the resource. That would be as you
have the example. However, as we're talking about standard slots (or at
least standard slot rails), we likely don't have node for the device in
the slot and can't add one since it is likely unknown what the device
is. In other cases, we'd define a connector or slot node, but there's
not really a way to do that given the PCI bus topology is already
defined. So I think the right place is the bridge node on the upstream
side of the slot/connector. So the 'pci@0,0' node in your case.

Rob

> brcm,scb-sizes:
> description: u64 giving the 64bit PCIe memory
> viewport size of a memory controller. There may be up to
> @@ -158,5 +162,28 @@ examples:
> <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
> brcm,enable-ssc;
> brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
> +
> + /* PCIe bridge */
> + pci@0,0 {
> + #address-cells = <3>;
> + #size-cells = <2>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + compatible = "pciclass,0604";
> + device_type = "pci";
> + ranges;
> +
> + /* PCIe endpoint */
> + pci-ep@0,0 {
> + assigned-addresses =
> + <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + compatible = "pci14e4,1688";
> + vpcie3v3-supply = <&vreg7>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges;
> + };
> + };
> };
> };
> --
> 2.17.1
>
>