From: Huang Rui <ray.huang@amd.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
Linux PM <linux-pm@vger.kernel.org>,
"Sharma, Deepak" <Deepak.Sharma@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"Limonciello, Mario" <Mario.Limonciello@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
"Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
"Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
"Du, Xiaojian" <Xiaojian.Du@amd.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
the arch/x86 maintainers <x86@kernel.org>
Subject: Re: [PATCH v5 03/22] ACPI: CPPC: implement support for SystemIO registers
Date: Fri, 17 Dec 2021 12:30:42 +0800 [thread overview]
Message-ID: <YbwScmyB6sml3onw@amd.com> (raw)
In-Reply-To: <CAJZ5v0iTnQYpj6aZBa8ZqUQN-TJCK0GLRhK1-mdXEX1iPpkjxA@mail.gmail.com>
On Fri, Dec 17, 2021 at 01:40:47AM +0800, Rafael J. Wysocki wrote:
> On Tue, Nov 30, 2021 at 1:37 PM Huang Rui <ray.huang@amd.com> wrote:
> >
> > From: Steven Noonan <steven@valvesoftware.com>
> >
> > According to the ACPI v6.2 (and later) specification, SystemIO can be
> > used for _CPC registers. This teaches cppc_acpi how to handle such
> > registers.
> >
> > This patch was tested using the amd_pstate driver on my Zephyrus G15
> > (model GA503QS) using the current version 410 BIOS, which uses
> > a SystemIO register for the HighestPerformance element in _CPC.
> >
> > Signed-off-by: Steven Noonan <steven@valvesoftware.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> > drivers/acpi/cppc_acpi.c | 46 +++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 43 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > index a85c351589be..ca62c3dc9899 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -746,9 +746,24 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> > goto out_free;
> > cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
> > }
> > + } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> > + if (gas_t->access_width < 1 || gas_t->access_width > 3) {
> > + /* 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit. SystemIO doesn't
>
> The comment format is not in agreement with the kernel coding style.
Will update it in V6.
>
> > + * implement 64-bit registers.
> > + */
> > + pr_debug("Invalid access width %d for SystemIO register\n",
> > + gas_t->access_width);
> > + goto out_free;
> > + }
> > + if (gas_t->address & ~0xFFFFULL) {
>
> It would be good to define a symbol for this mask and use it here
> instead of the raw vaue.
OK.
>
> > + /* SystemIO registers use 16-bit integer addresses */
> > + pr_debug("Invalid IO port %llu for SystemIO register\n",
> > + gas_t->address);
> > + goto out_free;
> > + }
> > } else {
> > if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
> > - /* Support only PCC ,SYS MEM and FFH type regs */
> > + /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
> > pr_debug("Unsupported register type: %d\n", gas_t->space_id);
> > goto out_free;
> > }
> > @@ -923,7 +938,20 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
> > }
> >
> > *val = 0;
> > - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
> > +
> > + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> > + u32 width = 8 << (reg->access_width - 1);
> > + acpi_status status;
> > +
> > + status = acpi_os_read_port((acpi_io_address)reg->address, (u32 *)val, width);
> > +
> > + if (status != AE_OK) {
>
> Please use ACPI_FAILURE() here and in the analogous check and below.
Fine, I will update this as well.
Thanks,
Ray
>
> > + pr_debug("Error: Failed to read SystemIO port %llx\n", reg->address);
> > + return -EFAULT;
> > + }
> > +
> > + return 0;
> > + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
> > vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
> > else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
> > vaddr = reg_res->sys_mem_vaddr;
> > @@ -962,7 +990,19 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
> > int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > struct cpc_reg *reg = ®_res->cpc_entry.reg;
> >
> > - if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
> > + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
> > + u32 width = 8 << (reg->access_width - 1);
> > + acpi_status status;
> > +
> > + status = acpi_os_write_port((acpi_io_address)reg->address, (u32)val, width);
> > +
> > + if (status != AE_OK) {
> > + pr_debug("Error: Failed to write SystemIO port %llx\n", reg->address);
> > + return -EFAULT;
> > + }
> > +
> > + return 0;
> > + } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
> > vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
> > else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
> > vaddr = reg_res->sys_mem_vaddr;
> > --
next prev parent reply other threads:[~2021-12-17 4:31 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 12:36 [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-11-30 12:36 ` [PATCH v5 01/22] x86/cpufeatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-11-30 12:36 ` [PATCH v5 02/22] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-12-16 17:23 ` Rafael J. Wysocki
2021-12-17 3:09 ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 03/22] ACPI: CPPC: implement support for SystemIO registers Huang Rui
2021-12-16 17:40 ` Rafael J. Wysocki
2021-12-17 4:30 ` Huang Rui [this message]
2021-11-30 12:36 ` [PATCH v5 04/22] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-11-30 12:36 ` [PATCH v5 05/22] ACPI: CPPC: add cppc enable register function Huang Rui
2021-11-30 12:36 ` [PATCH v5 06/22] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-12-16 17:59 ` Rafael J. Wysocki
2021-12-17 7:34 ` Huang Rui
2021-12-17 14:03 ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 07/22] cpufreq: amd: add fast switch function for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 08/22] cpufreq: amd: introduce the support for the processors with shared memory solution Huang Rui
2021-12-16 18:04 ` Rafael J. Wysocki
2021-12-17 7:37 ` Huang Rui
2021-11-30 12:36 ` [PATCH v5 09/22] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-12-16 18:12 ` Rafael J. Wysocki
2021-12-17 7:52 ` Huang Rui
2021-12-17 14:05 ` Rafael J. Wysocki
2021-11-30 12:36 ` [PATCH v5 10/22] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-11-30 12:36 ` [PATCH v5 11/22] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-11-30 12:36 ` [PATCH v5 12/22] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-11-30 12:36 ` [PATCH v5 13/22] cpupower: add AMD P-state capability flag Huang Rui
2021-11-30 12:36 ` [PATCH v5 14/22] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-11-30 12:36 ` [PATCH v5 15/22] cpupower: initial AMD P-state capability Huang Rui
2021-11-30 12:36 ` [PATCH v5 16/22] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-11-30 12:36 ` [PATCH v5 17/22] cpupower: introduce acpi cppc library Huang Rui
2021-11-30 12:36 ` [PATCH v5 18/22] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 19/22] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-11-30 12:36 ` [PATCH v5 20/22] cpupower: move print_speed function into misc helper Huang Rui
2021-11-30 12:36 ` [PATCH v5 21/22] cpupower: print amd-pstate information on cpupower Huang Rui
2021-11-30 12:36 ` [PATCH v5 22/22] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-12-16 18:20 ` [PATCH v5 00/22] cpufreq: introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YbwScmyB6sml3onw@amd.com \
--to=ray.huang@amd.com \
--cc=Alexander.Deucher@amd.com \
--cc=Deepak.Sharma@amd.com \
--cc=Jinzhou.Su@amd.com \
--cc=Mario.Limonciello@amd.com \
--cc=Nathan.Fontenot@amd.com \
--cc=Xiaojian.Du@amd.com \
--cc=bp@suse.de \
--cc=ggherdovich@suse.cz \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
--cc=rafael.j.wysocki@intel.com \
--cc=rafael@kernel.org \
--cc=skhan@linuxfoundation.org \
--cc=steven@valvesoftware.com \
--cc=viresh.kumar@linaro.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox