From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D259C433EF for ; Wed, 9 Feb 2022 22:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236038AbiBIWfR (ORCPT ); Wed, 9 Feb 2022 17:35:17 -0500 Received: from gmail-smtp-in.l.google.com ([23.128.96.19]:49832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236025AbiBIWfK (ORCPT ); Wed, 9 Feb 2022 17:35:10 -0500 Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFBA4E019269 for ; Wed, 9 Feb 2022 14:35:11 -0800 (PST) Received: by mail-oo1-xc2f.google.com with SMTP id 189-20020a4a03c6000000b003179d7b30d8so4220721ooi.2 for ; Wed, 09 Feb 2022 14:35:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7sNMbEN2ZWSKBSAKG7biB3FxMf95az/sXODaHaCSWMs=; b=xdcjIPjBdfsq47myDzGlv/zDnSvqcldTrssyKMmoNbBcmUw17fDaGp0J/7YeM0yqmg s8qWJDlGouztaI3L3dssm+Cpw12Gr8ov9SLFvidB+1pfLT8ol8I+JprQAoRBrzqqrboZ nbXLMNrQFM1FxTGR9rCmePKWeLdWhoR/y5dfoPvdJz9aFLZ+TN2pxPw6d9x/VIJuj36Z eNTwsOF1QO3RaM49fcz4iuxlbP58AFsMFNuprEf3paG49jotMgGznnttTKdpyvTJtONz AxIlSS+bv2EvMq+7ollItzv1rZG4cyXWmZORmzxdjX9tjb1Dc0LvVir9lQHsGl0NbMxu dDAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7sNMbEN2ZWSKBSAKG7biB3FxMf95az/sXODaHaCSWMs=; b=om84PQsyukY8g4jXBv+Y1rFzKxUomdAMPJsUww0bobZTLk5HGFApFe4azQwSOuuxOl jlVdo3sVhy732m5JbDQVjAoXDSvsr1zyrPgx9T5kcBB5i1/7WvOCpRsa38+1ac9rWBNn ASta+ahX8NB6QGFocT1yXVaHV7nBmwR7KUNU8j5XIOQMJcF7oqTl/q4hkEuFMOYhQyAl fYFlOkEMDVmKVEAGVirxoIJ7h9NuijYDG0XASWiXvuj4fbIqLt2t8/3aU3vk12PnyKk3 ao6jyYntv93SzXVuvLtuIJ7tRG9Gs3x5F8uaiuiPmRtswupJDpXiTiRQ6PHrEYjUINLS 931w== X-Gm-Message-State: AOAM5330QrUwlSRVNv2IWnSt+LKTmjScN3pO5eSXStlTGpEnzBEQCyFQ 3CwN5kD4ttK/QG6fASh95DJotA== X-Google-Smtp-Source: ABdhPJw6ZCPvGXCBpXm4rynDmp58kloRm/T18gaJuFBSN0X6h1u23KWWxaJ+mFJOT3PwydMvdL4l/A== X-Received: by 2002:a4a:e1cb:: with SMTP id n11mr1840337oot.46.1644446111200; Wed, 09 Feb 2022 14:35:11 -0800 (PST) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id s64sm7233725oos.0.2022.02.09.14.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Feb 2022 14:35:10 -0800 (PST) Date: Wed, 9 Feb 2022 16:35:08 -0600 From: Bjorn Andersson To: Taniya Das Cc: Stephen Boyd , Michael Turquette ? , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [v1 1/2] clk: qcom: gdsc: Use the default transition delay for GDSCs Message-ID: References: <20220209172513.17873-1-tdas@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220209172513.17873-1-tdas@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 09 Feb 11:25 CST 2022, Taniya Das wrote: > Do not update the transition delay and use the default reset values. > > Fixes: 45dd0e55317cc ("clk: qcom: Add support for GDSCs) > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/gdsc.c | 6 +++++- > drivers/clk/qcom/gdsc.h | 1 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index 7e1dd8ccfa38..e7b213450640 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -380,7 +380,11 @@ static int gdsc_init(struct gdsc *sc) > */ > mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | > EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK; > - val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; > + > + regmap_read(sc->regmap, sc->gdscr, &val); > + > + if (!(sc->flags & DEFAULT_TRANSITION_DELAY)) I dug a little bit more into this and noticed that on various platforms CLK_DIS_WAIT_VAL for the GPU_CX GDSC is supposed to be 8 (whereas both hw default and CLK_DIS_WAIT_VAL is 2). I'm not able to find anything helpful in the git log describing what the value does, but it seems that a "just use hw default" flag won't cut it for this scenario. Regards, Bjorn > + val |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; > ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); > if (ret) > return ret; > diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h > index d7cc4c21a9d4..1bd3ecdd0b0a 100644 > --- a/drivers/clk/qcom/gdsc.h > +++ b/drivers/clk/qcom/gdsc.h > @@ -53,6 +53,7 @@ struct gdsc { > #define ALWAYS_ON BIT(6) > #define RETAIN_FF_ENABLE BIT(7) > #define NO_RET_PERIPH BIT(8) > +#define DEFAULT_TRANSITION_DELAY BIT(9) > struct reset_controller_dev *rcdev; > unsigned int *resets; > unsigned int reset_count; > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. >