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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id l1-20020a4aa781000000b0031cf8e00738sm7916823oom.1.2022.03.02.09.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 09:50:15 -0800 (PST) Received: (nullmailer pid 3953295 invoked by uid 1000); Wed, 02 Mar 2022 17:50:13 -0000 Date: Wed, 2 Mar 2022 11:50:13 -0600 From: Rob Herring To: Medad CChien Cc: rric@kernel.org, james.morse@arm.com, tony.luck@intel.com, mchehab@kernel.org, bp@alien8.de, benjaminfair@google.com, yuenn@google.com, venture@google.com, KWLIU@nuvoton.com, YSCHU@nuvoton.com, JJLIU0@nuvoton.com, KFTING@nuvoton.com, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Medad CChien , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Subject: Re: [PATCH v2 2/3] dt-bindings: edac: npcm-edac.yaml Message-ID: References: <20220302092434.16625-1-ctcchien@nuvoton.com> <20220302092434.16625-3-ctcchien@nuvoton.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220302092434.16625-3-ctcchien@nuvoton.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 02, 2022 at 05:24:33PM +0800, Medad CChien wrote: > Add the device tree bindings for the EDAC driver npcm-edac. > > Signed-off-by: Medad CChien > --- > .../devicetree/bindings/edac/npcm-edac.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/npcm-edac.yaml > > diff --git a/Documentation/devicetree/bindings/edac/npcm-edac.yaml b/Documentation/devicetree/bindings/edac/npcm-edac.yaml > new file mode 100644 > index 000000000000..936e9787ec80 > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/npcm-edac.yaml nuvoton,npcm-memory-controller.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/edac/npcm-edac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton NPCM Memory Controller EDAC Drop 'EDAC' > + > +maintainers: > + - Medad CChien > + > +description: | > + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error > + correction check). > + > + The memory controller supports single bit error correction, double bit > + error detection (in-line ECC in which a section (1/8th) of the > + memory device used to store data is used for ECC storage). > + > + Note, the bootloader must configure ECC mode for the memory controller. > + > +properties: > + compatible: > + enum: > + - nuvoton,npcm8xx-memory-controller > + - nuvoton,npcm7xx-memory-controller Don't use wildcards in compatible strings. Use specific SoC. > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 1 > + items: > + - description: uncorrectable error interrupt > + - description: correctable error interrupt > + > + interrupt-names: > + minItems: 1 > + items: > + - const: ue > + - const: ce > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + #include > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + mc: memory-controller@f0824000 { > + compatible = "nuvoton,npcm7xx-memory-controller"; > + reg = <0x0 0xf0824000 0x0 0x1000>; > + interrupts = ; > + }; > + }; > + > -- > 2.17.1 >