RE: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer

Sanil, Shruthi
2022-02-23T07:49:39Z

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Wednesday, February 23, 2022 4:44 AM
> To: Sanil, Shruthi <shruthi.sanil@intel.com>
> Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org;
> andriy.shevchenko@linux.intel.com; mgross@linux.intel.com; Thokala,
> Srikanth <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai
> <lakshmi.bai.raja.subramanian@intel.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar@intel.com>
> Subject: Re: [PATCH v8 1/2] dt-bindings: timer: Add bindings for Intel Keem
> Bay SoC Timer
>
> On Tue, Feb 22, 2022 at 03:26:53PM +0530, shruthi.sanil@intel.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@intel.com>
> >
> > Add Device Tree bindings for the Timer IP, which can be used as
> > clocksource and clockevent device in the Intel Keem Bay SoC.
> >
> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
> > ---
> > .../bindings/timer/intel,keembay-timer.yaml | 128 ++++++++++++++++++
> > 1 file changed, 128 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> > new file mode 100644
> > index 000000000000..9e6d46ecc2dc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-
> timer.yaml
> > @@ -0,0 +1,128 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel Keem Bay SoC Timers
> > +
> > +maintainers:
> > + - Shruthi Sanil <shruthi.sanil@intel.com>
> > +
> > +description: |
> > + The Intel Keem Bay timer driver supports 1 free running counter and 8
> timers.
>
> Bindings describe the h/w, not what drivers support.

Sorry for adding the word driver here.
Actually the Keem Bay timer IP has 1 free running counter and 8 timers.
I'll correct the description explaining clearly that the above are the H/W details.

>
> > + Each timer is capable of generating inividual interrupt.
> > + Both the features are enabled through the timer general config register.
> > +
> > + The parent node represents the common general configuration details
> > + and the child nodes represents the counter and timers.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
>
> Don't need oneOf with only 1 entry.

OK, I'll correct it in my next patch.

>
> > + - enum:
> > + - intel,keembay-gpt-creg
> > + - const: simple-mfd
> > +
> > + reg:
> > + description: General configuration register address and length.
> > + maxItems: 1
> > +
> > + ranges: true
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - ranges
> > + - "#address-cells"
> > + - "#size-cells"
> > +
> > +patternProperties:
> > + "^counter@[0-9a-f]+$":
> > + description: Properties for Intel Keem Bay counter.
> > + type: object
> > + properties:
> > + compatible:
> > + oneOf:
>
> Don't need oneOf.

OK, I'll correct it in my next patch.

>
> > + - items:
> > + - enum:
> > + - intel,keembay-counter
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - clocks
> > +
> > + "^timer@[0-9a-f]+$":
> > + description: Properties for Intel Keem Bay timer
> > + type: object
> > + properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - intel,keembay-timer
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #define KEEM_BAY_A53_TIM
> > +
> > + soc {
> > + #address-cells = <0x2>;
> > + #size-cells = <0x2>;
> > +
> > + gpt@20331000 {
> > + compatible = "intel,keembay-gpt-creg", "simple-mfd";
>
> It looks like you are splitting things based on Linux implementation details.
> Does this h/w block have different combinations of timers and counters? If
> not, then you don't need the child nodes at all. There's plenty of h/w blocks
> that get used as both a clocksource and clockevent.
>

Yes, the Timer H/W block has 1 free running counter and 8 timers.
These timers and counter are enabled using a common configuration register.
Hence we have a parent node which has the details of this common configuration register
And the child nodes with their register and interrupt details.

> Maybe I already raised this, but assume I don't remember and this patch
> needs to address any questions I already asked.

All the review comments given by you in the series of this patch are addressed.

In the example below, I have just added the details of one timer.
But in actual we have a total of 8 timers.
I can update all the 8 if that's required to be updated.

>
> > + reg = <0x0 0x20331000 0x0 0xc>;
> > + ranges = <0x0 0x0 0x20330000 0xF0>;
> > + #address-cells = <0x1>;
> > + #size-cells = <0x1>;
> > +
> > + counter@e8 {
> > + compatible = "intel,keembay-counter";
> > + reg = <0xe8 0x8>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > +
> > + timer@30 {
> > + compatible = "intel,keembay-timer";
> > + reg = <0x30 0xc>;
> > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.17.1
> >
> >