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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id c26-20020a056830349a00b005af30960c75sm1268657otu.38.2022.02.25.08.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 08:04:32 -0800 (PST) Received: (nullmailer pid 1008598 invoked by uid 1000); Fri, 25 Feb 2022 16:04:30 -0000 Date: Fri, 25 Feb 2022 10:04:30 -0600 From: Rob Herring To: "Peng Fan (OSS)" Cc: aisheng.dong@nxp.com, festevam@gmail.com, shawnguo@kernel.org, stefan@agner.ch, kernel@pengutronix.de, linus.walleij@linaro.org, linux-imx@nxp.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: imx93: Add pinctrl binding Message-ID: References: <20220215082006.790843-1-peng.fan@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220215082006.790843-1-peng.fan@oss.nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 15, 2022 at 04:20:05PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > Add pinctrl binding doc for i.MX93 > > Signed-off-by: Peng Fan > --- > .../bindings/pinctrl/fsl,imx93-pinctrl.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml > new file mode 100644 > index 000000000000..95c87ea4c5c8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: GPL-2.0 Dual license. checkpatch will tell you this and which ones. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale IMX93 IOMUX Controller > + > +maintainers: > + - Peng Fan > + > +description: > + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory > + for common binding part and usage. > + > +properties: > + compatible: > + const: fsl,imx93-iomuxc > + > + reg: > + maxItems: 1 > + > +# Client device subnode's properties > +patternProperties: > + 'grp$': > + type: object > + description: > + Pinctrl node's client devices use subnodes for desired pin configuration. > + Client device subnodes use below standard properties. > + > + properties: > + fsl,pins: > + description: > + each entry consists of 6 integers and represents the mux and config > + setting for one pin. The first 5 integers + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can > + be found in . The last > + integer CONFIG is the pad setting value like pull-up on this pin. Please > + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + items: > + items: > + - description: | > + "mux_reg" indicates the offset of mux register. > + - description: | > + "conf_reg" indicates the offset of pad configuration register. > + - description: | > + "input_reg" indicates the offset of select input register. > + - description: | > + "mux_val" indicates the mux value to be applied. > + - description: | > + "input_val" indicates the select input value to be applied. > + - description: | > + "pad_setting" indicates the pad configuration value to be applied. > + > + > + required: > + - fsl,pins > + > + additionalProperties: false > + > +allOf: > + - $ref: "pinctrl.yaml#" Move this above 'properties' > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + # Pinmux controller node > + - | > + iomuxc: pinctrl@443c0000 { > + compatible = "fsl,imx93-iomuxc"; > + reg = <0x30330000 0x10000>; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = > + <0x48 0x1f8 0x41c 0x1 0x0 0x49>, > + <0x4c 0x1fc 0x418 0x1 0x0 0x49>; > + }; > + }; > + > +... > -- > 2.25.1 > >