From: Rob Herring <robh@kernel.org>
To: Hector Martin <marcan@marcan.st>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Sven Peter <sven@svenpeter.dev>,
Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Mark Kettenis <mark.kettenis@xs4all.nl>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2
Date: Fri, 25 Feb 2022 14:19:44 -0600 [thread overview]
Message-ID: <Yhk54H989MfhGMcu@robh.at.kernel.org> (raw)
In-Reply-To: <20220224130741.63924-3-marcan@marcan.st>
On Thu, Feb 24, 2022 at 10:07:36PM +0900, Hector Martin wrote:
> This new incompatible revision of the AIC peripheral introduces
> multi-die support. This binding is based on apple,aic, but
> changes interrupt-cells to add a new die argument.
>
> Also adds an apple,event-reg property to specify the offset of the event
> register. Inexplicably, the capability registers allow us to compute
> other register offsets, but not this one. This allows us to keep
> forward-compatibility with future SoCs that will likely implement
> different die counts, thus shifting the event register. Apple do the
> same thing in their device tree...
>
> Signed-off-by: Hector Martin <marcan@marcan.st>
> ---
> .../interrupt-controller/apple,aic2.yaml | 99 +++++++++++++++++++
> MAINTAINERS | 2 +-
> 2 files changed, 100 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml
> new file mode 100644
> index 000000000000..311900613b9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Apple Interrupt Controller 2
> +
> +maintainers:
> + - Hector Martin <marcan@marcan.st>
> +
> +description: |
> + The Apple Interrupt Controller 2 is a simple interrupt controller present on
> + Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
> +
> + It provides the following features:
> +
> + - Level-triggered hardware IRQs wired to SoC blocks
> + - Single mask bit per IRQ
> + - Automatic masking on event delivery (auto-ack)
> + - Software triggering (ORed with hw line)
> + - Automatic prioritization (single event/ack register per CPU, lower IRQs =
> + higher priority)
> + - Automatic masking on ack
> + - Support for multiple dies
> +
> + This device also represents the FIQ interrupt sources on platforms using AIC,
> + which do not go through a discrete interrupt controller. It also handles
> + FIQ-based Fast IPIs.
> +
> +properties:
> + compatible:
> + items:
> + - const: apple,t6000-aic
> + - const: apple,aic2
I feel I was sold on Apple doesn't change h/w and we're the 2nd chip in
and the h/w changed. Just my musings, but aic3 will be rejected. :(
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 4
> + description: |
> + The 1st cell contains the interrupt type:
> + - 0: Hardware IRQ
> + - 1: FIQ
> +
> + The 2nd cell contains the die ID.
> +
> + The next cell contains the interrupt number.
> + - HW IRQs: interrupt number
> + - FIQs:
> + - 0: physical HV timer
> + - 1: virtual HV timer
> + - 2: physical guest timer
> + - 3: virtual guest timer
> +
> + The last cell contains the interrupt flags. This is normally
> + IRQ_TYPE_LEVEL_HIGH (4).
> +
> + reg:
> + description: |
> + Specifies base physical address and size of the AIC registers.
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + apple,event-reg:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Specifies the offset of the event register, which lies after all the
> + implemented die register sets, page aligned. This is not computable from
> + capability register values, so we have to specify it explicitly.
If this is last, then couldn't it be a 2nd 'reg' entry?
'page aligned' is ambiguous. I assume that means 16K since that's what
Apple uses, but I might assume 4K not knowing that.
> +
> +required:
> + - compatible
> + - '#interrupt-cells'
> + - interrupt-controller
> + - reg
> + - apple,event-reg
> +
> +additionalProperties: false
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aic: interrupt-controller@28e100000 {
> + compatible = "apple,t6000-aic", "apple,aic2";
> + #interrupt-cells = <4>;
> + interrupt-controller;
> + reg = <0x2 0x8e100000 0x0 0x10000>;
> + apple,event-reg = <0xc000>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aa0f6cbb634e..ad887ec7e96b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1806,7 +1806,7 @@ T: git https://github.com/AsahiLinux/linux.git
> F: Documentation/devicetree/bindings/arm/apple.yaml
> F: Documentation/devicetree/bindings/arm/apple/*
> F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
> -F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml
> +F: Documentation/devicetree/bindings/interrupt-controller/apple,*
> F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml
> F: Documentation/devicetree/bindings/pci/apple,pcie.yaml
> F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
> --
> 2.33.0
>
>
next prev parent reply other threads:[~2022-02-25 20:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-24 13:07 [PATCH v2 0/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-24 13:07 ` [PATCH v2 1/7] PCI: apple: Change MSI handling to handle 4-cell AIC fwspec form Hector Martin
2022-02-24 13:07 ` [PATCH v2 2/7] dt-bindings: interrupt-controller: apple,aic2: New binding for AICv2 Hector Martin
2022-02-25 20:19 ` Rob Herring [this message]
2022-02-25 21:58 ` Hector Martin
2022-03-07 11:35 ` Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 3/7] irqchip/apple-aic: Add Fast IPI support Hector Martin
2022-02-25 14:39 ` Marc Zyngier
2022-02-27 15:33 ` Hector Martin
2022-03-07 11:35 ` Marc Zyngier
2022-02-24 13:07 ` [PATCH v2 4/7] irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs Hector Martin
2022-02-24 13:07 ` [PATCH v2 5/7] irqchip/apple-aic: Dynamically compute register offsets Hector Martin
2022-02-24 13:07 ` [PATCH v2 6/7] irqchip/apple-aic: Support multiple dies Hector Martin
2022-02-24 13:07 ` [PATCH v2 7/7] irqchip/apple-aic: Add support for AICv2 Hector Martin
2022-02-25 15:27 ` Marc Zyngier
2022-02-25 22:05 ` Hector Martin
2022-02-24 18:26 ` [PATCH v2 0/7] " Mark Rutland
2022-02-24 19:06 ` Marc Zyngier
2022-02-25 4:27 ` Hector Martin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Yhk54H989MfhGMcu@robh.at.kernel.org \
--to=robh@kernel.org \
--cc=alyssa@rosenzweig.io \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marcan@marcan.st \
--cc=mark.kettenis@xs4all.nl \
--cc=maz@kernel.org \
--cc=sven@svenpeter.dev \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox