[PATCH v4 7/7] ARM64: mt8183: Add support of APU to mt8183

Alexandre Bailon
2022-03-04T16:15:56Z

This adds the support of APU to mt8183.

Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
---
.../boot/dts/mediatek/mt8183-pumpkin.dts | 50 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 40 +++++++++++++++
2 files changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index ee912825cfc6..155c89c998d3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -37,6 +37,42 @@ scp_mem_reserved: scp_mem_region@50000000 {
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
+
+ vdev0buffer: vdev0buffer@52900000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x52900000 0 0x4000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@52904000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x52904000 0 0x2000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@52906000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x52906000 0 0x2000>;
+ no-map;
+ };
+
+ vdev1buffer: vdev1buffer@52908000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x52908000 0 0x4000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@5290C000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x5290C000 0 0x2000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@5290E000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x5290E000 0 0x2000>;
+ no-map;
+ };
};

leds {
@@ -381,3 +417,17 @@ &scp {
&dsi0 {
status = "disabled";
};
+
+&apu0 {
+ memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>;
+ memory-region-names = "vdev0buffer", "vdev0vring0", "vdev0vring1";
+ memory-region-da = <0x6fff8000>, <0x6fffc000>, <0x6fffe000>;
+ status = "okay";
+};
+
+&apu1 {
+ memory-region = <&vdev1buffer>, <&vdev1vring0>, <&vdev1vring1>;
+ memory-region-names = "vdev1buffer", "vdev1vring0", "vdev1vring1";
+ memory-region-da = <0x6fff0000>, <0x6fff4000>, <0x6fff6000>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index ba4584faca5a..cb02f57e000d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1542,12 +1542,52 @@ ipu_adl: syscon@19010000 {
#clock-cells = <1>;
};

+ apu0: apu@0x19100000 {
+ compatible = "mediatek,mt8183-apu";
+ reg = <0 0x19180000 0 0x14000>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_LOW>;
+
+ iommus = <&iommu M4U_PORT_IMG_IPUO>,
+ <&iommu M4U_PORT_IMG_IPU3O>,
+ <&iommu M4U_PORT_IMG_IPUI>;
+
+ clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>,
+ <&ipu_core0 CLK_IPU_CORE0_IPU>,
+ <&ipu_core0 CLK_IPU_CORE0_JTAG>;
+
+ clock-names = "axi", "ipu", "jtag";
+
+ power-domains = <&spm MT8183_POWER_DOMAIN_VPU_CORE0>;
+
+ status = "disabled";
+ };
+
ipu_core0: syscon@19180000 {
compatible = "mediatek,mt8183-ipu_core0", "syscon";
reg = <0 0x19180000 0 0x1000>;
#clock-cells = <1>;
};

+ apu1: apu@19200000 {
+ compatible = "mediatek,mt8183-apu";
+ reg = <0 0x19280000 0 0x14000>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_LOW>;
+
+ iommus = <&iommu M4U_PORT_CAM_IPUO>,
+ <&iommu M4U_PORT_CAM_IPU2O>,
+ <&iommu M4U_PORT_CAM_IPU3O>;
+
+ clocks = <&ipu_core0 CLK_IPU_CORE1_AXI>,
+ <&ipu_core0 CLK_IPU_CORE1_IPU>,
+ <&ipu_core0 CLK_IPU_CORE1_JTAG>;
+
+ clock-names = "axi", "ipu", "jtag";
+
+ power-domains = <&spm MT8183_POWER_DOMAIN_VPU_CORE1>;
+
+ status = "disabled";
+ };
+
ipu_core1: syscon@19280000 {
compatible = "mediatek,mt8183-ipu_core1", "syscon";
reg = <0 0x19280000 0 0x1000>;
--
2.34.1