From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C01FC433F5 for ; Thu, 3 Mar 2022 10:48:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232482AbiCCKs7 (ORCPT ); Thu, 3 Mar 2022 05:48:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231405AbiCCKs6 (ORCPT ); Thu, 3 Mar 2022 05:48:58 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4649913CEEF; Thu, 3 Mar 2022 02:48:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646304493; x=1677840493; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=XERL7zQnkfENm2cJG9WqtvSSN/OYkhjEjtnM4+TkMjc=; b=PJtT/4CCe8zIFceXZVouAaaFcAspOTQzXtQ6M0P2Jt6e5OUi+z2/bKbb KrPlNftsahfI9pCbN7JsaJ/M0slhuCiO/BhYh2b8NW0SzZarU+vf+j+Kf EyfxJnCGm/qBL1ryd3TFrVMvVJS88fMjuVCrzdiSw4bOGAt3b4+cdjl56 0nH6DPKnfKQ4wAbdpJIdYfIHvpsSuVAJVBnMgvBJY/KfE2H55pMmPdiUt BBKZz7YwL72mhJgVDF29Ek9O8EYfFg+mjKbGKcYWXH1I7D7Wv5ONwl8A9 LCfImoUGFqrg9JMF2RIZW98rqIJ2no5C2bQYTUUgg8USWXHclYc+vLqqd Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10274"; a="241061517" X-IronPort-AV: E=Sophos;i="5.90,151,1643702400"; d="scan'208";a="241061517" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2022 02:48:12 -0800 X-IronPort-AV: E=Sophos;i="5.90,151,1643702400"; d="scan'208";a="640136529" Received: from smile.fi.intel.com ([10.237.72.59]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2022 02:48:10 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1nPizT-00AkGn-Hz; Thu, 03 Mar 2022 12:47:23 +0200 Date: Thu, 3 Mar 2022 12:47:23 +0200 From: "andriy.shevchenko@linux.intel.com" To: Daniel Lezcano Cc: "Sanil, Shruthi" , "tglx@linutronix.de" , "robh+dt@kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "mgross@linux.intel.com" , "Thokala, Srikanth" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" Subject: Re: [PATCH v8 2/2] clocksource: Add Intel Keem Bay timer support Message-ID: References: <20220222095654.9097-1-shruthi.sanil@intel.com> <20220222095654.9097-3-shruthi.sanil@intel.com> <91653d8d-1dc6-0170-2c3c-1187b0bad899@linaro.org> <23f86de0-3869-ee22-812d-ba610bac48b3@linaro.org> <3ff11b85-249f-2f47-cbc4-41d2ab6d168f@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 03, 2022 at 11:17:33AM +0100, Daniel Lezcano wrote: > On 03/03/2022 07:18, Sanil, Shruthi wrote: > > > > > > > > + if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) { + > > > > > > > > pr_err("%pOF: Prescaler is not enabled\n", np); > > > > > > > > + ret = -ENODEV; + } > > > > > > > > > > > > > > Why bail out instead of enabling the prescalar ? > > > > > > > > > > > > Because it is a secure register and it would be updated by > > > > > > the bootloader. > > > > > Should it be considered as a firmware bug ? > > > > > > > > No. This is a common driver across products in the series and > > > > enablement of this bit depends on the project requirements. > > > > Hence > > > > to be sure from driver, we added this check to avoid > > > > initialization of the driver in the case where it cannot be > > > > functional. > > > > > > I'm not sure to get the meaning of 'project requirements' but (for > > > my understanding) why not describe the timer in the DT for such > > > projects? > > > > > > > OK, I understand your point now. We can control the driver > > initialization from device tree binding rather than add a check in > > the driver. But isn't it good to have a check, if enabling of the bit > > is missed out in the FW? This can help in debugging. > > So if the description is in the DT but the prescaler bit is not enabled then > the firmware is buggy, IIUC. Yeah, this check would help, may be add more > context in the error message, eg. "Firmware has not enabled the prescaler > bit" or something like that For this we also use a FW_BUG prefix to printf()-like functions. -- With Best Regards, Andy Shevchenko