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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id f8-20020a4a8908000000b0032472938f95sm4241174ooi.17.2022.03.22.07.39.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 07:39:45 -0700 (PDT) Received: (nullmailer pid 1981681 invoked by uid 1000); Tue, 22 Mar 2022 14:39:43 -0000 Date: Tue, 22 Mar 2022 09:39:43 -0500 From: Rob Herring To: Robin Murphy , Marc Zyngier Cc: dann frazier , "linux-kernel@vger.kernel.org" , linux-arm-kernel , PCI , Toan Le , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , =?iso-8859-1?Q?St=E9phane?= Graber , Android Kernel Team Subject: Re: [PATCH v2 0/2] PCI: xgene: Restore working PCIe functionnality Message-ID: References: <20220321104843.949645-1-maz@kernel.org> <87h77rxnyl.wl-maz@kernel.org> <87fsnbxgau.wl-maz@kernel.org> <61809b8f-acaa-bae2-ac5e-aa47c55eea23@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <61809b8f-acaa-bae2-ac5e-aa47c55eea23@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 22, 2022 at 01:16:35PM +0000, Robin Murphy wrote: > On 2022-03-21 20:06, Robin Murphy wrote: > > On 2022-03-21 19:21, Marc Zyngier wrote: > > > On Mon, 21 Mar 2022 18:03:27 +0000, > > > Rob Herring wrote: > > > > > > > > On Mon, Mar 21, 2022 at 11:36 AM Marc Zyngier wrote: > > > > > > > > > > On Mon, 21 Mar 2022 15:17:34 +0000, > > > > > Rob Herring wrote: > > > > > > > > > > > > On Mon, Mar 21, 2022 at 5:49 AM Marc Zyngier wrote: > > > > > > > > > > > > > For XGene-1, I'd still like to understand what the issue is. Reverting > > > > > > the first fix and fixing 'dma-ranges' should have fixed it. I need a > > > > > > dump of how the IB registers are initialized in both cases. I'm not > > > > > > saying changing 'dma-ranges' in the firmware is going to be required > > > > > > here. There's a couple of other ways we could fix that without a > > > > > > firmware change, but first I need to understand why it broke. > > > > > > > > > > Reverting 6dce5aa59e0b was enough for me, without changing anything > > > > > else. > > > > > > > > Meaning c7a75d07827a didn't matter for you. I'm not sure that it would. > > > > > > > > Can you tell me what 'dma-ranges' contains on your system? > > > > > > Each pcie node (all 5 of them) has: > > > > > > dma-ranges = <0x42000000 0x80 0x00 0x80 0x00 0x00 0x80000000 > > >                0x42000000 0x00 0x00 0x00 0x00 0x80 0x00>; This is the same as what Stéphane has for Merlin. So c7a75d07827a ("PCI: xgene: Fix IB window setup") should have fixed Mustang. > > > > Hmm, is there anyone other than iommu-dma who actually depends on the > > resource list being sorted in ascending order of bus address? I recall > > at the time I pushed for creating the list in sorted order as it was the > > simplest and most efficient option, but there's no technical reason we > > couldn't create it in as-found order and defer the sorting until > > iova_reserve_pci_windows() (at worst that could even operate on a > > temporary copy if need be). It's just more code, which didn't need to > > exist without a good reason, but if this is one then exist it certainly > > may. > > Taking a closer look, the Cadence driver is already re-sorting the list > for its own setup, so iommu-dma can't assume the initial sort is > preserved and needs to do its own anyway. Does the (untested) diff below > end up helping X-Gene also? There's no IOMMU on X-Gene 1 or 2 based on the upstream dts files, so how would this matter? Rob