[PATCH 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant

Heiko Stuebner
2022-03-07T22:46:34Z

This series is based on the alternatives changes done in my svpbmt series
and thus also depends on Atish's isa-extension parsing series.

It implements using the cache-management instructions from the Zicbom-
extension to handle cache flush, etc actions on platforms needing them.

SoCs using cpu cores from T-Head like the Allwinne D1 implement a
different set of cache instructions. But while they are different,
instructions they provide the same functionality, so a variant can
easly hook into the existing alternatives mechanism on those.

Heiko Stuebner (2):
riscv: Implement Zicbom-based cache management operations
riscv: implement cache-management errata for T-Head SoCs

arch/riscv/Kconfig | 8 +++
arch/riscv/Kconfig.erratas | 10 ++++
arch/riscv/errata/thead/errata.c | 5 ++
arch/riscv/include/asm/errata_list.h | 78 +++++++++++++++++++++++++++-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 17 ++++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/dma-noncoherent.c | 61 ++++++++++++++++++++++
9 files changed, 180 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/mm/dma-noncoherent.c

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2.30.2