[PATCH 01/14] dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml

Philipp Zabel
2022-04-07T15:44:21Z

Convert the device tree bindings for the Amlogic audio memory arbiter
controller to YAML schema to allow participating in DT validation.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../reset/amlogic,meson-axg-audio-arb.txt | 22 --------
.../reset/amlogic,meson-axg-audio-arb.yaml | 56 +++++++++++++++++++
2 files changed, 56 insertions(+), 22 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml

diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
deleted file mode 100644
index 43e580ef64ba..000000000000
--- a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Amlogic audio memory arbiter controller
-
-The Amlogic Audio ARB is a simple device which enables or
-disables the access of Audio FIFOs to DDR on AXG based SoC.
-
-Required properties:
-- compatible: 'amlogic,meson-axg-audio-arb' or
- 'amlogic,meson-sm1-audio-arb'
-- reg: physical base address of the controller and length of memory
- mapped region.
-- clocks: phandle to the fifo peripheral clock provided by the audio
- clock controller.
-- #reset-cells: must be 1.
-
-Example on the A113 SoC:
-
-arb: reset-controller@280 {
- compatible = "amlogic,meson-axg-audio-arb";
- reg = <0x0 0x280 0x0 0x4>;
- #reset-cells = <1>;
- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
-};
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml
new file mode 100644
index 000000000000..704a502adc5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/amlogic,meson-axg-audio-arb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic audio memory arbiter controller
+
+maintainers:
+ - Jerome Brunet <jbrunet@baylibre.com>
+
+description: The Amlogic Audio ARB is a simple device which enables or disables
+ the access of Audio FIFOs to DDR on AXG based SoC.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-axg-audio-arb
+ - amlogic,meson-sm1-audio-arb
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: |
+ phandle to the fifo peripheral clock provided by the audio clock
+ controller.
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ // on the A113 SoC:
+ #include <dt-bindings/clock/axg-audio-clkc.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ arb: reset-controller@280 {
+ compatible = "amlogic,meson-axg-audio-arb";
+ reg = <0x0 0x280 0x0 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+ };
+ };
--
2.30.2