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Thu, 14 Apr 2022 20:56:58 -0700 Date: Thu, 14 Apr 2022 20:56:57 -0700 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , Subject: Re: [PATCH] iommu/arm-smmu-v3: Align size in __arm_smmu_tlb_inv_range Message-ID: References: <20220413041745.35174-1-nicolinc@nvidia.com> <37c02fc4-d793-b003-f612-206c987a8a42@arm.com> <13c91dfb-c540-ed8d-daa7-eab7207df221@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <13c91dfb-c540-ed8d-daa7-eab7207df221@arm.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d7e54d91-7d75-4c56-9330-08da1e93fe40 X-MS-TrafficTypeDiagnostic: DM5PR12MB1659:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9BKyqcuZfiQriq6gTJtPb570vqKJYFVhOcRT/IuENCCW4mfTQb+MHGZ9MTMO8qCuWpQXI1m9NkI3AGjuRg9PRNIhAKznL1nWEouheoQ8nbTHS5zC59ptiNQTEdhtMfd+UKDtJlO0flLTSc9ReA4jfAJiFxb9kOdV/WujTA53TLjIfDWEnbzwBlq5GPQSn8GLAAMKU6ypwjzOYd/AkuS4HRbhvt4aFBXhbqc5Utl7Ne8JzJkNs42So96f9vn4xCZZ26sFB1W+av40o9l+pig4p3+PeP7f1CnpGb2dniPophG6840C04KqT8Vi4KW92wVGLLpUE3wBIjr1UhQKgiPsu7mMvvAnPjRJf7DsY5BeWUhU5TTvKQx4uB+zX8PTyESDWM+UFl2GrSm0+wPoeoY6sJAI0WCfZYxUxYGyl1PXwpHr3MSU7LEA4vBLW2cxxSta5f8FkWYfwTH/0BCJ8wn6ShR04UBvNikaHlf57gi8fRqm6TCnbiS2rrcbeCWhb3103RsWcyT7UucQSDtPSdK/z6gOj4671/0LkHrexo+Y+fBQcRE8qU7MVvhYIKDjhj+oLLhxp0ytJ6/XoA4/mivPgK5rEWSGkZB+nDa9LPtMMKMmldOcUS6zqhvfRoAfJQNvq0XegkDcoSnXZAJMWqFJOMP32HS86wqdg7SE2Rn+wVxyblwt6iczhOiv/d5m1GsDVm6kCzWFyFTSgexeTOnbyQ== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(7416002)(508600001)(53546011)(55016003)(81166007)(82310400005)(5660300002)(9686003)(40460700003)(86362001)(356005)(6916009)(54906003)(2906002)(316002)(36860700001)(186003)(26005)(47076005)(8676002)(33716001)(4326008)(70586007)(70206006)(336012)(426003)(83380400001)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2022 03:56:59.9454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7e54d91-7d75-4c56-9330-08da1e93fe40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1659 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 14, 2022 at 11:32:38AM +0100, Robin Murphy wrote: > External email: Use caution opening links or attachments > > > On 2022-04-13 21:19, Nicolin Chen wrote: > > Hi Robin, > > > > On Wed, Apr 13, 2022 at 02:40:31PM +0100, Robin Murphy wrote: > > > On 2022-04-13 05:17, Nicolin Chen wrote: > > > > To calculate num_pages, the size should be aligned with > > > > "page size", determined by the tg value. Otherwise, its > > > > following "while (iova < end)" might become an infinite > > > > loop if unaligned size is slightly greater than 1 << tg. > > > > > > Hmm, how does a non-page-aligned invalidation request get generated in > > > the first place? > > > > I don't have the testing environment because it was a bug, > > reported by a client who uses SVA feature on top of SMMU. > > > > But judging from the log, the non-page-aligned inv request > > was coming from an likely incorrect end address, e.g. > > { start = 0xff10000, end = 0xff20000 } > > So the size turned out to be 0x10001, unaligned. > > > > I don't have a full call trace on hand right now to see if > > upper callers are doing something wrong when calculate the > > end address, though I've asked the owner to check. > > > > By looking at the call trace within arm_smmu_* functions: > > __arm_smmu_tlb_inv_range > > arm_smmu_tlb_inv_range_asid > > arm_smmu_mm_invalidate_range > > {from mm_notifier_* functions} > > > > There's no address alignment check. Although I do think we > > should fix the source who passes down the non-page-aligned > > parameter, the SMMU driver shouldn't silently dead loop if > > a set of unaligned inputs are given, IMHO. > > Oh, sure, I'm not saying we definitely don't need to fix anything, I'd > just like to get a better understanding of *what* we're fixing. I'd have > (naively) expected the mm layer to give us page-aligned quantities even > in the SVA notifier case, so if we've got a clear off-by-one somewhere > in that path we should fix that before just blindly over-invalidating to > paper over it; I see. Yea, definitely should fix the source too. I've asked the owner to track it down. I sent the change, thinking that we could do it in parallel. > if we still also want to be robust at the SMMU driver end > just in case, something like "if (WARN_ON(num_pages == 0)) num_pages = > 1;" might be more appropriate. However if it turns out that we *can* > actually end up with unsanitised input from some userspace unmap > interface getting this far, then a silent fixup is the best option, but > if so I'd still like to confirm that we're rounding in the same > direction as whoever touched the pagetables (since it can't have been us). I see. I'll give an update once I have the debugging result. Thanks! Nic