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[82.192.242.114]) by smtp.gmail.com with ESMTPSA id v17-20020a1709060b5100b006f38cf075cbsm273241ejg.104.2022.04.28.11.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 11:43:09 -0700 (PDT) Sender: Salvatore Bonaccorso Date: Thu, 28 Apr 2022 20:43:07 +0200 From: Salvatore Bonaccorso To: Thomas Gleixner Cc: Jeremi Piotrowski , Dusty Mabe , Stefan Roese , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Michal Simek , Marek Vasut , x86@kernel.org, maz@kernel.org, Andrew Cooper , Juergen Gross , Noah Meyerhans Subject: Re: [tip: irq/urgent] PCI/MSI: Mask MSI-X vectors only on success Message-ID: References: <20211210161025.3287927-1-sr@denx.de> <163948488617.23020.3934435568065766936.tip-bot2@tip-bot2> <43418c23-5efd-4d14-706f-f536c504b75a@denx.de> <87v8uuwhs4.ffs@tglx> <87wnf9uxnw.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87wnf9uxnw.ffs@tglx> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thomas, On Thu, Apr 28, 2022 at 03:48:03PM +0200, Thomas Gleixner wrote: > On Wed, Apr 27 2022 at 19:35, Thomas Gleixner wrote: > > On Wed, Apr 27 2022 at 09:59, Salvatore Bonaccorso wrote: > > XEN guests do not use the common PCI mask/unmask machinery which would > > unmask the interrupt on request_irq(). > > > > So I assume that the following happens: > > > > Guest Hypervisor > > > > msix_capabilities_init() > > .... > > alloc_irq() > > xen_magic() -> alloc_msix_interrupt() > > request_irq() > > > > msix_mask_all() -> trap > > do_magic() > > request_irq() > > unmask() > > xen_magic() > > unmask_evtchn() -> do_more_magic() > > > > So I assume further that msix_mask_all() actually is able to mask the > > interrupts in the hardware (ctrl word of the vector table) despite the > > hypervisor having allocated and requested the interrupt already. > > > > Nothing in XEN_HVM handles PCI/MSI[-X] mask/unmask in the guest, so I > > really have to ask why XEN_HVM does not disable PCI/MSI[-X] masking like > > XEN_PV does. I can only assume the answer is voodoo... > > > > Maybe the XEN people have some more enlightened answers to that. > > So I was talking to Juergen about this and he agrees, that for the case > where a XEN HVM guest uses the PIRQ/Eventchannel mechanism PCI/MSI[-X] > masking should be disabled like it is done for XEN PV. > > Why the hypervisor grants the mask write is still mysterious, but I > leave that to the folks who can master the XEN voodoo. > > I'll send out a patch in minute. Thank you. We are having Noah Meyerhans now testing the patch and he will report back if it works (Cc'ed here now). Regards, Salvatore