From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE1FEC433EF for ; Fri, 29 Apr 2022 22:23:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381426AbiD2W1H (ORCPT ); Fri, 29 Apr 2022 18:27:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236352AbiD2W1E (ORCPT ); Fri, 29 Apr 2022 18:27:04 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 576FFDC9B9 for ; Fri, 29 Apr 2022 15:23:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Transfer-Encoding:Content-Disposition: Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:From: Sender:Reply-To:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Content-Disposition: In-Reply-To:References; bh=iOIJ1Kr+mtstrHF5VkGvwL6t99fgCHEkIg1mM2125l4=; b=hI Qmahk/3EuTVhlkQAshosyxgUq1CeOh1x684yCnU5NNyKy+l9SlL4Pmpc4sfKlWaj+4+3bx3LPSwdn VuCBOGvCOXryUJgVYy1KMJeC+zvGvQX0HbemDKesSNArm1AEA7ODXDL06Z7kIa4MOQES5hHv8gMGF sA+IHsYa8VA1WGI=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1nkZ1S-000YOK-PN; Sat, 30 Apr 2022 00:23:34 +0200 Date: Sat, 30 Apr 2022 00:23:34 +0200 From: Andrew Lunn To: Pali =?iso-8859-1?Q?Roh=E1r?= Cc: Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x Message-ID: References: <20220425113706.29310-1-pali@kernel.org> <20220429130524.vs6mlzvotvaortbw@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220429130524.vs6mlzvotvaortbw@pali> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 29, 2022 at 03:05:24PM +0200, Pali Rohár wrote: > On Friday 29 April 2022 14:23:08 Andrew Lunn wrote: > > On Mon, Apr 25, 2022 at 01:37:05PM +0200, Pali Rohár wrote: > > > Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific > > > and on new Armada platforms it has different meaning. It does not configure > > > Performance Counter Overflow interrupt masking. So do not touch this > > > register on non-A370/XP platforms (A375, A38x and A39x). > > > > Hi Pali > > > > Do the Armada 375, 38x and 39x have an over flow interrupt? I assume > > not. > > Hello! According to documentation there is something named performance > counter interrupt, but it is in different register... and this register > is not per-cpu. O.K, not something which can be quickly added. > > Does this need a fixes tag? Should it be back ported in stable? > > git blame show that this functionality appeared in commit 28da06dfd9e4 > ("irqchip: armada-370-xp: Enable the PMU interrupts"). It is more a question of: o It must fix a real bug that bothers people (not a, “This could be a problem…” type thing). >From https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html Have you seen bad things happen because of this? Andrew