From: Mark Brown <broonie@kernel.org>
To: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
kernel@pengutronix.de, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org, NXP Linux Team <linux-imx@nxp.com>,
Fabio Estevam <festevam@gmail.com>
Subject: Re: [PATCH v1] spi: imx: mx51-ecspi: fix clk polarity and phase configuration for CS > 4
Date: Thu, 26 May 2022 16:51:18 +0100 [thread overview]
Message-ID: <Yo+h9ssyWfb19aey@sirena.org.uk> (raw)
In-Reply-To: <20220523073143.778664-1-o.rempel@pengutronix.de>
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On Mon, May 23, 2022 at 09:31:43AM +0200, Oleksij Rempel wrote:
> Fix support for boards with more then 4 chip select lines. Other wise if
> CS > 4 is used, we will write trash to the clk configuration register.
This doesn't apply against current code, please check and resend.
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prev parent reply other threads:[~2022-05-26 15:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 7:31 [PATCH v1] spi: imx: mx51-ecspi: fix clk polarity and phase configuration for CS > 4 Oleksij Rempel
2022-05-23 13:27 ` Mark Brown
2022-05-23 15:40 ` Oleksij Rempel
2022-05-26 15:51 ` Mark Brown [this message]
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