From: Jisheng Zhang <jszhang@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrey Ryabinin <ryabinin.a.a@gmail.com>,
Alexander Potapenko <glider@google.com>,
Andrey Konovalov <andreyknvl@gmail.com>,
Dmitry Vyukov <dvyukov@google.com>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
Alexandre Ghiti <alexandre.ghiti@canonical.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
kasan-dev@googlegroups.com
Subject: Re: [PATCH v2 2/4] riscv: introduce unified static key mechanism for CPU features
Date: Wed, 18 May 2022 00:33:52 +0800 [thread overview]
Message-ID: <YoPOcHvhWEqeEwzo@xhacker> (raw)
In-Reply-To: <CAK9=C2VJ-+bu20+QOfKrq6cEBE93Yi21U=zU9AKOSQi1GGHWiA@mail.gmail.com>
On Tue, May 17, 2022 at 09:31:50AM +0530, Anup Patel wrote:
> On Mon, May 16, 2022 at 11:02 PM Jisheng Zhang <jszhang@kernel.org> wrote:
> >
...
> > Currently, RISCV_ISA_EXT_MAX equals to 64 while the base ID is 26.
> > In those 26 base IDs, only F/D and V need static key, it means
> > we waste at least 24 static keys.
>
> If you want to save space of unused static keys then there are other
> ways.
>
> For example, you can create a small static key array which has
> many-to-one relation with the ISA extension numbers. For ISA extension
"any problem in computer science can be solved with another layer of
indirection" ;)
I see your points, thanks very much! But I think the array should
be a static inline function to make use of compiler optimization to
avoid the array references for performance. And the static key check
maybe used in modules, I want to export less vars.
I'm cooking the patches, will send out for review soon.
> which are always ON or always OFF, we can use fixed FALSE and
> TRUE keys. Something like below.
>
> enum riscv_isa_ext_key {
> RISCV_ISA_EXT_KEY_FALSE = 0,
> RISCV_ISA_EXT_KEY_TRUE,
> RISCV_ISA_EXT_KEY_FLOAD, /* For 'F' and 'D' */
> RISCV_ISA_EXT_KEY_VECTOR, /* For all vector extensions */
> RISCV_ISA_EXT_KEY_SVINVAL,
> RISCV_ISA_EXT_KEY_SSCOFPMT,
> RISCV_ISA_EXT_KEY_MAX,
> };
>
> extern unsigned char __riscv_isa_ext_id2key[RISCV_ISA_EXT_ID_MAX];
> extern struct static_key_false __riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
>
> static __always_inline bool __riscv_isa_extension_keycheck(unsigned int ext)
> {
> if (RISCV_ISA_EXT_ID_MAX <= ext)
> return false;
> return static_branch_unlikely(&__riscv_isa_ext_keys[__riscv_isa_ext_id2key[ext]]);
> }
> #define riscv_isa_extension_keycheck(ext) \
> __riscv_isa_extension_keycheck(RISCV_ISA_EXT_##ext)
>
next prev parent reply other threads:[~2022-05-17 16:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-08 16:07 [PATCH v2 0/4] unified way to use static key and optimize pgtable_l4_enabled Jisheng Zhang
2022-05-08 16:07 ` [PATCH v2 1/4] riscv: mm: init: make pt_ops_set_[early|late|fixmap] static Jisheng Zhang
2022-05-09 3:51 ` Anup Patel
2022-05-08 16:07 ` [PATCH v2 2/4] riscv: introduce unified static key mechanism for CPU features Jisheng Zhang
2022-05-09 3:47 ` Anup Patel
2022-05-09 14:41 ` Jisheng Zhang
2022-05-12 6:29 ` Atish Patra
2022-05-15 7:15 ` Jisheng Zhang
2022-05-15 14:49 ` Anup Patel
2022-05-16 17:24 ` Jisheng Zhang
2022-05-17 4:01 ` Anup Patel
2022-05-17 16:33 ` Jisheng Zhang [this message]
2022-05-08 16:07 ` [PATCH v2 3/4] riscv: replace has_fpu() with system_supports_fpu() Jisheng Zhang
2022-05-09 4:01 ` Anup Patel
2022-05-08 16:07 ` [PATCH v2 4/4] riscv: convert pgtable_l4|[l5]_enabled to static key Jisheng Zhang
2022-05-09 3:59 ` Anup Patel
2022-05-09 4:37 ` [PATCH v2 0/4] unified way to use static key and optimize pgtable_l4_enabled Anup Patel
2022-05-09 14:26 ` Jisheng Zhang
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