From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B1A7C433F5 for ; Wed, 18 May 2022 16:16:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240000AbiERQQp (ORCPT ); Wed, 18 May 2022 12:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239976AbiERQQn (ORCPT ); Wed, 18 May 2022 12:16:43 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 092ACA76D4 for ; Wed, 18 May 2022 09:16:41 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id a23-20020a17090acb9700b001df4e9f4870so2564175pju.1 for ; Wed, 18 May 2022 09:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=27J+LsUtyeeYy/GvJkk2tphV2jBbsCOsrmpZjooJvdA=; b=WsFMsQRAqPFYtDRXv1eq/d16y4WXmvGrQzz4CAO9ARgrPBnZudm/BdIonig9LJyFcm x6L1zSSnkCAOWz2YA0yASGUB+S/LnV93goRZsCwFI/c0oM6Wt6HovjUhwpPIhHwnAmgf 0UULa2rgpV/0NpYuJBZ1n9Y7Z3J0NyCqw3cQu4ZP70oCUpqlb8b8MsNZ0F22EDY2ZbA3 5E1hyQWNsllEe7cLvGs3pzHDGEMwvrxA4n0ilcZn7OsnEXZa9Xik24fr3nohv7oQ4WX1 CW6+uDBt2U+dmO+Q5ct+H8Au3VCnLrnBY51f3Z4vRidqf2HwVg5OVps7L3et5gtGQ2aA EKFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=27J+LsUtyeeYy/GvJkk2tphV2jBbsCOsrmpZjooJvdA=; b=KqbdwOCGfod8n1bo2nrNrHDZNkoPISnWr6llifjLn5WvsVjJt08mZ5uRNaEjyWi+dm tT6dqFC7k4GDmqrAJzmwnNbpAQ3jjciukBOrtTG2vQTRqQG+YbPQcOk2r/j10vfT0jYa vC+dkhvkmFcwkoiVhwqbpQFOyHspmjGRDt0b+kT848wb+X3iKEVlu8+Zl34xPQ3OfZFv 6NeKoQMy/f98sdn+bCUHj10cHJQrDQo9GEa/ZEEClHwbBe9BWfERo99pprvrGdR0YJ1C 96G4Ovy2O/9YXXEa8fn2TjqCJ/JJQcI/YzAKFQdGoVh1Y+cVm3EGi9MOamgdRVp9aHQo Lf5A== X-Gm-Message-State: AOAM531VOpYpdbf6yzRkc7OX+J5oRFZ7NEaYDbXYALXHetNAoskYqGXs psskEXEgcGDLzYmmJ7eC0z16nw== X-Google-Smtp-Source: ABdhPJzlMzaxzyxYIp0EtYqROS3OrIc3ty0dMgOLbrexh3oQF/2zOIfjp3/5KS2qx0kdvnbCWlOOjg== X-Received: by 2002:a17:90a:7441:b0:1df:5f54:502c with SMTP id o1-20020a17090a744100b001df5f54502cmr770638pjk.129.1652890600319; Wed, 18 May 2022 09:16:40 -0700 (PDT) Received: from google.com (157.214.185.35.bc.googleusercontent.com. [35.185.214.157]) by smtp.gmail.com with ESMTPSA id 4-20020a170902e9c400b0015e8d4eb264sm1893016plk.174.2022.05.18.09.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 09:16:39 -0700 (PDT) Date: Wed, 18 May 2022 16:16:35 +0000 From: Sean Christopherson To: John Allen Cc: Yang Weijiang , pbonzini@redhat.com, jmattson@google.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, yu.c.zhang@linux.intel.com Subject: Re: [PATCH v15 07/14] KVM: VMX: Emulate reads and writes to CET MSRs Message-ID: References: <20210203113421.5759-1-weijiang.yang@intel.com> <20210203113421.5759-8-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 18, 2022, John Allen wrote: > On Wed, Feb 03, 2021 at 07:34:14PM +0800, Yang Weijiang wrote: > > + case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: > > + if (!cet_is_ssp_msr_accessible(vcpu, msr_info)) > > + return 1; > > + if ((data & GENMASK(2, 0)) || is_noncanonical_address(data, vcpu)) > > Sorry to revive this old thread. I'm working on the corresponding SVM > bits for shadow stack and I noticed the above check. Why isn't this > GENMASK(1, 0)? The *SSP MSRs should be a 4-byte aligned canonical > address meaning that just bits 1 and 0 should always be zero. I was > looking through the previous versions of the set and found that this > changed between versions 11 and 12, but I don't see any discussion > related to this on the list. Huh. I'm not entirely sure what to make of the SDM's wording: The linear address written must be aligned to 8 bytes and bits 2:0 must be 0 (hardware requires bits 1:0 to be 0). Looking at the rest of the CET stuff, I believe requiring 8-byte alignment is correct, and that the "hardware requires" blurb is trying to call out that the SSP stored in hardware will always be 4-byte aligned but not necessarily 8-byte aligned in order to play nice with 32-bit/compatibility mode. But "base" addresses that come from software, e.g. via MSRs and whatnot, must always be 8-byte aligned.