* [PATCH 1/2] perf list: Add IBM z16 event description for s390 @ 2022-05-30 10:56 Thomas Richter 2022-05-30 10:56 ` [PATCH 2/2] perf list: Update event description for s390 machines to latest level Thomas Richter 2022-05-31 14:56 ` [PATCH 1/2] perf list: Add IBM z16 event description for s390 Ian Rogers 0 siblings, 2 replies; 5+ messages in thread From: Thomas Richter @ 2022-05-30 10:56 UTC (permalink / raw) To: linux-kernel, linux-perf-users, acme Cc: svens, gor, sumanthk, hca, Thomas Richter [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset=y, Size: 35264 bytes --] Update IBM z16 counter description using document SA23-2260-07: "The Load-Program-Parameter and the CPU-Measurement Facilities" released in May, 2022, to include counter definitions for IBM z16 counter sets: * Basic counter set * Problem/user counter set * Crypto counter set Use document SA23-2261-07: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" released on April 29, 2022 to include counter definitions for IBM z16 * Extended counter set * MT-Diagnostic counter set Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> --- .../pmu-events/arch/s390/cf_z16/basic.json | 58 +++ .../pmu-events/arch/s390/cf_z16/crypto6.json | 142 +++++ .../pmu-events/arch/s390/cf_z16/extended.json | 492 ++++++++++++++++++ .../arch/s390/cf_z16/transaction.json | 7 + tools/perf/pmu-events/arch/s390/mapfile.csv | 1 + 5 files changed, 700 insertions(+) create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/basic.json create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/extended.json create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/transaction.json diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/basic.json b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json new file mode 100644 index 000000000000..1023d47028ce --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json @@ -0,0 +1,58 @@ +[ + { + "Unit": "CPU-M-CF", + "EventCode": "0", + "EventName": "CPU_CYCLES", + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "1", + "EventName": "INSTRUCTIONS", + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "2", + "EventName": "L1I_DIR_WRITES", + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "3", + "EventName": "L1I_PENALTY_CYCLES", + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "4", + "EventName": "L1D_DIR_WRITES", + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "5", + "EventName": "L1D_PENALTY_CYCLES", + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "32", + "EventName": "PROBLEM_STATE_CPU_CYCLES", + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "33", + "EventName": "PROBLEM_STATE_INSTRUCTIONS", + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." + } +] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json new file mode 100644 index 000000000000..8b4380b8e489 --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json @@ -0,0 +1,142 @@ +[ + { + "Unit": "CPU-M-CF", + "EventCode": "64", + "EventName": "PRNG_FUNCTIONS", + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "65", + "EventName": "PRNG_CYCLES", + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "66", + "EventName": "PRNG_BLOCKED_FUNCTIONS", + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "67", + "EventName": "PRNG_BLOCKED_CYCLES", + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "68", + "EventName": "SHA_FUNCTIONS", + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "69", + "EventName": "SHA_CYCLES", + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "70", + "EventName": "SHA_BLOCKED_FUNCTIONS", + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "71", + "EventName": "SHA_BLOCKED_CYCLES", + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "72", + "EventName": "DEA_FUNCTIONS", + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "73", + "EventName": "DEA_CYCLES", + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "74", + "EventName": "DEA_BLOCKED_FUNCTIONS", + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "75", + "EventName": "DEA_BLOCKED_CYCLES", + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "76", + "EventName": "AES_FUNCTIONS", + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "77", + "EventName": "AES_CYCLES", + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "78", + "EventName": "AES_BLOCKED_FUNCTIONS", + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "79", + "EventName": "AES_BLOCKED_CYCLES", + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "80", + "EventName": "ECC_FUNCTION_COUNT", + "BriefDescription": "ECC Function Count", + "PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "81", + "EventName": "ECC_CYCLES_COUNT", + "BriefDescription": "ECC Cycles Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cryptography (ECC) functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "82", + "EventName": "ECC_BLOCKED_FUNCTION_COUNT", + "BriefDescription": "Ecc Blocked Function Count", + "PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "83", + "EventName": "ECC_BLOCKED_CYCLES_COUNT", + "BriefDescription": "ECC Blocked Cycles Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU." + } +] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json new file mode 100644 index 000000000000..c306190fc06f --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json @@ -0,0 +1,492 @@ +[ + { + "Unit": "CPU-M-CF", + "EventCode": "128", + "EventName": "L1D_RO_EXCL_WRITES", + "BriefDescription": "L1D Read-only Exclusive Writes", + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "129", + "EventName": "DTLB2_WRITES", + "BriefDescription": "DTLB2 Writes", + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "130", + "EventName": "DTLB2_MISSES", + "BriefDescription": "DTLB2 Misses", + "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "131", + "EventName": "CRSTE_1MB_WRITES", + "BriefDescription": "One Megabyte CRSTE writes", + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "132", + "EventName": "DTLB2_GPAGE_WRITES", + "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "134", + "EventName": "ITLB2_WRITES", + "BriefDescription": "ITLB2 Writes", + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "135", + "EventName": "ITLB2_MISSES", + "BriefDescription": "ITLB2 Misses", + "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "137", + "EventName": "TLB2_PTE_WRITES", + "BriefDescription": "TLB2 Page Table Entry Writes", + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "138", + "EventName": "TLB2_CRSTE_WRITES", + "BriefDescription": "TLB2 Combined Region and Segment Entry Writes", + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "139", + "EventName": "TLB2_ENGINES_BUSY", + "BriefDescription": "TLB2 Engines Busy", + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "140", + "EventName": "TX_C_TEND", + "BriefDescription": "Completed TEND instructions in constrained TX mode", + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "141", + "EventName": "TX_NC_TEND", + "BriefDescription": "Completed TEND instructions in non-constrained TX mode", + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "143", + "EventName": "L1C_TLB2_MISSES", + "BriefDescription": "L1C TLB2 Misses", + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "145", + "EventName": "DCW_REQ", + "BriefDescription": "Directory Write Level 1 Data Cache from Cache", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "146", + "EventName": "DCW_REQ_IV", + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "147", + "EventName": "DCW_REQ_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "148", + "EventName": "DCW_REQ_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "149", + "EventName": "DCW_ON_CHIP", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "150", + "EventName": "DCW_ON_CHIP_IV", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "151", + "EventName": "DCW_ON_CHIP_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "152", + "EventName": "DCW_ON_CHIP_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "153", + "EventName": "DCW_ON_MODULE", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "154", + "EventName": "DCW_ON_DRAWER", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "155", + "EventName": "DCW_OFF_DRAWER", + "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "156", + "EventName": "DCW_ON_CHIP_MEMORY", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "157", + "EventName": "DCW_ON_MODULE_MEMORY", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "158", + "EventName": "DCW_ON_DRAWER_MEMORY", + "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "159", + "EventName": "DCW_OFF_DRAWER_MEMORY", + "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory", + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "160", + "EventName": "IDCW_ON_MODULE_IV", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "161", + "EventName": "IDCW_ON_MODULE_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "162", + "EventName": "IDCW_ON_MODULE_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "163", + "EventName": "IDCW_ON_DRAWER_IV", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "164", + "EventName": "IDCW_ON_DRAWER_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "165", + "EventName": "IDCW_ON_DRAWER_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "166", + "EventName": "IDCW_OFF_DRAWER_IV", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "167", + "EventName": "IDCW_OFF_DRAWER_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "168", + "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit", + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "169", + "EventName": "ICW_REQ", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "170", + "EventName": "ICW_REQ_IV", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "171", + "EventName": "ICW_REQ_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "172", + "EventName": "ICW_REQ_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "173", + "EventName": "ICW_ON_CHIP", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "174", + "EventName": "ICW_ON_CHIP_IV", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "175", + "EventName": "ICW_ON_CHIP_CHIP_HIT", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "176", + "EventName": "ICW_ON_CHIP_DRAWER_HIT", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "177", + "EventName": "ICW_ON_MODULE", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "178", + "EventName": "ICW_ON_DRAWER", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "179", + "EventName": "ICW_OFF_DRAWER", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "180", + "EventName": "ICW_ON_CHIP_MEMORY", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "181", + "EventName": "ICW_ON_MODULE_MEMORY", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "182", + "EventName": "ICW_ON_DRAWER_MEMORY", + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "183", + "EventName": "ICW_OFF_DRAWER_MEMORY", + "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory", + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "224", + "EventName": "BCD_DFP_EXECUTION_SLOTS", + "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions", + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "225", + "EventName": "VX_BCD_EXECUTION_SLOTS", + "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions", + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "226", + "EventName": "DECIMAL_INSTRUCTIONS", + "BriefDescription": "Decimal instruction dispatched", + "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "232", + "EventName": "LAST_HOST_TRANSLATIONS", + "BriefDescription": "Last host translation done", + "PublicDescription": "Last Host Translation done" + }, + { + "Unit": "CPU-M-CF", + "EventCode": "244", + "EventName": "TX_NC_TABORT", + "BriefDescription": "Aborted transactions in unconstrained TX mode", + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "245", + "EventName": "TX_C_TABORT_NO_SPECIAL", + "BriefDescription": "Aborted transactions in constrained TX mode", + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "246", + "EventName": "TX_C_TABORT_SPECIAL", + "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "248", + "EventName": "DFLT_ACCESS", + "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit", + "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit" + }, + { + "Unit": "CPU-M-CF", + "EventCode": "253", + "EventName": "DFLT_CYCLES", + "BriefDescription": "Cycles CPU is using Deflate unit", + "PublicDescription": "Cycles CPU is using Deflate unit" + }, + { + "Unit": "CPU-M-CF", + "EventCode": "256", + "EventName": "SORTL", + "BriefDescription": "Count SORTL instructions", + "PublicDescription": "Increments by one for every SORT LISTS instruction executed." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "265", + "EventName": "DFLT_CC", + "BriefDescription": "Increments DEFLATE CONVERSION CALL", + "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "266", + "EventName": "DFLT_CCFINISH", + "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", + "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "267", + "EventName": "NNPA_INVOCATIONS", + "BriefDescription": "NNPA Total invocations", + "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "268", + "EventName": "NNPA_COMPLETIONS", + "BriefDescription": "NNPA Total completions", + "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "269", + "EventName": "NNPA_WAIT_LOCK", + "BriefDescription": "Cycles spent obtaining NNPA lock", + "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "270", + "EventName": "NNPA_HOLD_LOCK", + "BriefDescription": "Cycles spent holding NNPA lock", + "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "448", + "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", + "BriefDescription": "Cycle count with one thread active", + "PublicDescription": "Cycle count with one thread active" + }, + { + "Unit": "CPU-M-CF", + "EventCode": "449", + "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", + "BriefDescription": "Cycle count with two threads active", + "PublicDescription": "Cycle count with two threads active" + } +] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json new file mode 100644 index 000000000000..1a0034f79f73 --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -0,0 +1,7 @@ +[ + { + "BriefDescription": "Transaction count", + "MetricName": "transaction", + "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + } +] diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv index 61641a3480e0..a918e1af77a5 100644 --- a/tools/perf/pmu-events/arch/s390/mapfile.csv +++ b/tools/perf/pmu-events/arch/s390/mapfile.csv @@ -5,3 +5,4 @@ Family-model,Version,Filename,EventType ^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$,1,cf_z13,core ^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core ^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core +^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core -- 2.36.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] perf list: Update event description for s390 machines to latest level 2022-05-30 10:56 [PATCH 1/2] perf list: Add IBM z16 event description for s390 Thomas Richter @ 2022-05-30 10:56 ` Thomas Richter 2022-05-31 14:57 ` Ian Rogers 2022-05-31 14:56 ` [PATCH 1/2] perf list: Add IBM z16 event description for s390 Ian Rogers 1 sibling, 1 reply; 5+ messages in thread From: Thomas Richter @ 2022-05-30 10:56 UTC (permalink / raw) To: linux-kernel, linux-perf-users, acme Cc: svens, gor, sumanthk, hca, Thomas Richter Update all s390 event counter description to the latest level as described in the documents 1. SA23-2260-07: "The Load-Program-Parameter and the CPU-Measurement Facilities." released on May, 2022 for the following counter sets: * Basic counter set * Crypto counter set * MT-Diagnostic counter set 2. SA23-2261-07: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" released on April 29, 2022. for the following counter sets: * Extended counter set * MT-Diagnostic counter set Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> --- .../pmu-events/arch/s390/cf_z10/basic.json | 48 ++++---- .../pmu-events/arch/s390/cf_z10/crypto.json | 64 +++++----- .../pmu-events/arch/s390/cf_z10/extended.json | 36 +++--- .../pmu-events/arch/s390/cf_z13/basic.json | 48 ++++---- .../pmu-events/arch/s390/cf_z13/crypto.json | 64 +++++----- .../pmu-events/arch/s390/cf_z13/extended.json | 100 +++++++-------- .../pmu-events/arch/s390/cf_z14/basic.json | 32 ++--- .../pmu-events/arch/s390/cf_z14/crypto.json | 64 +++++----- .../pmu-events/arch/s390/cf_z14/extended.json | 102 ++++++++-------- .../pmu-events/arch/s390/cf_z15/basic.json | 32 ++--- .../pmu-events/arch/s390/cf_z15/crypto.json | 114 ------------------ .../pmu-events/arch/s390/cf_z15/crypto6.json | 112 +++++++++++++++++ .../pmu-events/arch/s390/cf_z15/extended.json | 108 ++++++++--------- .../pmu-events/arch/s390/cf_z196/basic.json | 48 ++++---- .../pmu-events/arch/s390/cf_z196/crypto.json | 64 +++++----- .../arch/s390/cf_z196/extended.json | 44 +++---- .../pmu-events/arch/s390/cf_zec12/basic.json | 48 ++++---- .../pmu-events/arch/s390/cf_zec12/crypto.json | 64 +++++----- .../arch/s390/cf_zec12/extended.json | 66 +++++----- 19 files changed, 628 insertions(+), 630 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/s390/cf_z15/crypto.json diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json index 783de7f1aeaa..9bd20a5f47af 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json @@ -3,84 +3,84 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "34", "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", - "BriefDescription": "Problem-State L1I Directory Writes", - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "35", "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1I Penalty Cycles", - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "36", "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", - "BriefDescription": "Problem-State L1D Directory Writes", - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "37", "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1D Penalty Cycles", - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json index 3f28007d3892..a8d391ddeb8c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json +++ b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json @@ -3,112 +3,112 @@ "Unit": "CPU-M-CF", "EventCode": "64", "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "65", "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "66", "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "67", "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "68", "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "69", "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "70", "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "71", "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "72", "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "73", "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "74", "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "75", "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "76", "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "77", "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "78", "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "79", "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json index 86bd8ba9391d..bf6a9811e014 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json @@ -4,125 +4,125 @@ "EventCode": "128", "EventName": "L1I_L2_SOURCED_WRITES", "BriefDescription": "L1I L2 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache." }, { "Unit": "CPU-M-CF", "EventCode": "129", "EventName": "L1D_L2_SOURCED_WRITES", "BriefDescription": "L1D L2 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache." }, { "Unit": "CPU-M-CF", "EventCode": "130", "EventName": "L1I_L3_LOCAL_WRITES", "BriefDescription": "L1I L3 Local Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)." }, { "Unit": "CPU-M-CF", "EventCode": "131", "EventName": "L1D_L3_LOCAL_WRITES", "BriefDescription": "L1D L3 Local Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)." }, { "Unit": "CPU-M-CF", "EventCode": "132", "EventName": "L1I_L3_REMOTE_WRITES", "BriefDescription": "L1I L3 Remote Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)." }, { "Unit": "CPU-M-CF", "EventCode": "133", "EventName": "L1D_L3_REMOTE_WRITES", "BriefDescription": "L1D L3 Remote Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)." }, { "Unit": "CPU-M-CF", "EventCode": "134", "EventName": "L1D_LMEM_SOURCED_WRITES", "BriefDescription": "L1D Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "L1I_LMEM_SOURCED_WRITES", "BriefDescription": "L1I Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "136", "EventName": "L1D_RO_EXCL_WRITES", "BriefDescription": "L1D Read-only Exclusive Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "L1I_CACHELINE_INVALIDATES", "BriefDescription": "L1I Cacheline Invalidates", - "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache" + "PublicDescription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the same CPU as the Level-1 Instruction Cache." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "ITLB1_WRITES", "BriefDescription": "ITLB1 Writes", - "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "DTLB1_WRITES", "BriefDescription": "DTLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "142", "EventName": "TLB2_CRSTE_HPAGE_WRITES", "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "ITLB1_MISSES", "BriefDescription": "ITLB1 Misses", - "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress" + "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "DTLB1_MISSES", "BriefDescription": "DTLB1 Misses", - "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress" + "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "L2C_STORES_SENT", "BriefDescription": "L2C Stores Sent", - "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache" + "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json index 783de7f1aeaa..9bd20a5f47af 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json @@ -3,84 +3,84 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "34", "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", - "BriefDescription": "Problem-State L1I Directory Writes", - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "35", "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1I Penalty Cycles", - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "36", "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", - "BriefDescription": "Problem-State L1D Directory Writes", - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "37", "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1D Penalty Cycles", - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json index 3f28007d3892..a8d391ddeb8c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json @@ -3,112 +3,112 @@ "Unit": "CPU-M-CF", "EventCode": "64", "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "65", "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "66", "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "67", "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "68", "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "69", "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "70", "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "71", "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "72", "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "73", "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "74", "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "75", "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "76", "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "77", "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "78", "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "79", "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json index 1a5e4f89c57e..99c1b93a7e36 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json @@ -11,7 +11,7 @@ "EventCode": "129", "EventName": "DTLB1_WRITES", "BriefDescription": "DTLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." }, { "Unit": "CPU-M-CF", @@ -25,7 +25,7 @@ "EventCode": "131", "EventName": "DTLB1_HPAGE_WRITES", "BriefDescription": "DTLB1 One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." }, { "Unit": "CPU-M-CF", @@ -39,63 +39,63 @@ "EventCode": "133", "EventName": "L1D_L2D_SOURCED_WRITES", "BriefDescription": "L1D L2D Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." }, { "Unit": "CPU-M-CF", "EventCode": "134", "EventName": "ITLB1_WRITES", "BriefDescription": "ITLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "ITLB1_MISSES", "BriefDescription": "ITLB1 Misses", - "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress" + "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress." }, { "Unit": "CPU-M-CF", "EventCode": "136", "EventName": "L1I_L2I_SOURCED_WRITES", "BriefDescription": "L1I L2I Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "TLB2_CRSTE_HPAGE_WRITES", "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "TX_C_TEND", "BriefDescription": "Completed TEND instructions in constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "TX_NC_TEND", "BriefDescription": "Completed TEND instructions in non-constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", @@ -109,273 +109,273 @@ "EventCode": "144", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "L1D_ONNODE_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Node L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "L1D_ONNODE_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Node L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "149", "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "151", "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "154", "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "156", "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "157", "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "158", "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES", "BriefDescription": "L1D On-Node Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory." }, { "Unit": "CPU-M-CF", "EventCode": "159", "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES", "BriefDescription": "L1D On-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "160", "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "161", "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES", "BriefDescription": "L1D On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "162", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "163", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "164", "EventName": "L1I_ONNODE_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "165", "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "166", "EventName": "L1I_ONNODE_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Node L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "167", "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "168", "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "169", "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "170", "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "171", "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "172", "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "173", "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "174", "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "175", "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "176", "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES", "BriefDescription": "L1I On-Node Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory." }, { "Unit": "CPU-M-CF", "EventCode": "177", "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES", "BriefDescription": "L1I On-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "178", "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "179", "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES", "BriefDescription": "L1I On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "218", "EventName": "TX_NC_TABORT", "BriefDescription": "Aborted transactions in non-constrained TX mode", - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "219", "EventName": "TX_C_TABORT_NO_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", "EventCode": "220", "EventName": "TX_C_TABORT_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json index fc762e9f1d6e..1023d47028ce 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json @@ -3,56 +3,56 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json index 3f28007d3892..a8d391ddeb8c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json @@ -3,112 +3,112 @@ "Unit": "CPU-M-CF", "EventCode": "64", "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "65", "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "66", "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "67", "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "68", "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "69", "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "70", "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "71", "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "72", "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "73", "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "74", "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "75", "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "76", "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "77", "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "78", "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "79", "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json index 4942b20a1ea1..ad40cc4f9727 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json @@ -4,357 +4,357 @@ "EventCode": "128", "EventName": "L1D_RO_EXCL_WRITES", "BriefDescription": "L1D Read-only Exclusive Writes", - "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "129", "EventName": "DTLB2_WRITES", "BriefDescription": "DTLB2 Writes", - "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for what was provided for the DTLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "130", "EventName": "DTLB2_MISSES", "BriefDescription": "DTLB2 Misses", - "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle" + "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "131", "EventName": "DTLB2_HPAGE_WRITES", "BriefDescription": "DTLB2 One-Megabyte Page Writes", - "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done" + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done." }, { "Unit": "CPU-M-CF", "EventCode": "132", "EventName": "DTLB2_GPAGE_WRITES", "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", - "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "133", "EventName": "L1D_L2D_SOURCED_WRITES", "BriefDescription": "L1D L2D Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." }, { "Unit": "CPU-M-CF", "EventCode": "134", "EventName": "ITLB2_WRITES", "BriefDescription": "ITLB2 Writes", - "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "ITLB2_MISSES", "BriefDescription": "ITLB2 Misses", - "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle" + "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "136", "EventName": "L1I_L2I_SOURCED_WRITES", "BriefDescription": "L1I L2I Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB" + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB" + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "TLB2_ENGINES_BUSY", "BriefDescription": "TLB2 Engines Busy", - "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle" + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "TX_C_TEND", "BriefDescription": "Completed TEND instructions in constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "TX_NC_TEND", "BriefDescription": "Completed TEND instructions in non-constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "143", "EventName": "L1C_TLB2_MISSES", "BriefDescription": "L1C TLB2 Misses", - "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress" + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." }, { "Unit": "CPU-M-CF", "EventCode": "144", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D On-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "149", "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "151", "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "154", "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "156", "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "157", "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "158", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO", "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "162", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "163", "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "164", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "165", "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "166", "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I On-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "167", "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "168", "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "169", "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I Off-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "170", "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "171", "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "172", "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "173", "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "174", "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "175", "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "224", "EventName": "BCD_DFP_EXECUTION_SLOTS", "BriefDescription": "BCD DFP Execution Slots", - "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT" + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." }, { "Unit": "CPU-M-CF", "EventCode": "225", "EventName": "VX_BCD_EXECUTION_SLOTS", "BriefDescription": "VX BCD Execution Slots", - "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG" + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG." }, { "Unit": "CPU-M-CF", "EventCode": "226", "EventName": "DECIMAL_INSTRUCTIONS", "BriefDescription": "Decimal Instructions", - "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP" + "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." }, { "Unit": "CPU-M-CF", "EventCode": "232", "EventName": "LAST_HOST_TRANSLATIONS", "BriefDescription": "Last host translation done", - "PublicDescription": "Last Host Translation done" + "PublicDescription": "Last Host Translation done." }, { "Unit": "CPU-M-CF", "EventCode": "243", "EventName": "TX_NC_TABORT", "BriefDescription": "Aborted transactions in non-constrained TX mode", - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "244", "EventName": "TX_C_TABORT_NO_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", "EventCode": "245", "EventName": "TX_C_TABORT_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/basic.json b/tools/perf/pmu-events/arch/s390/cf_z15/basic.json index fc762e9f1d6e..1023d47028ce 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/basic.json @@ -3,56 +3,56 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json deleted file mode 100644 index 3f28007d3892..000000000000 --- a/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json +++ /dev/null @@ -1,114 +0,0 @@ -[ - { - "Unit": "CPU-M-CF", - "EventCode": "64", - "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "65", - "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "66", - "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "67", - "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "68", - "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "69", - "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "70", - "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "71", - "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "72", - "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "73", - "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "74", - "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "75", - "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "76", - "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "77", - "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "78", - "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" - }, - { - "Unit": "CPU-M-CF", - "EventCode": "79", - "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" - } -] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json b/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json index ad79189050a0..8b4380b8e489 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json @@ -1,4 +1,116 @@ [ + { + "Unit": "CPU-M-CF", + "EventCode": "64", + "EventName": "PRNG_FUNCTIONS", + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "65", + "EventName": "PRNG_CYCLES", + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "66", + "EventName": "PRNG_BLOCKED_FUNCTIONS", + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "67", + "EventName": "PRNG_BLOCKED_CYCLES", + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "68", + "EventName": "SHA_FUNCTIONS", + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "69", + "EventName": "SHA_CYCLES", + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "70", + "EventName": "SHA_BLOCKED_FUNCTIONS", + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "71", + "EventName": "SHA_BLOCKED_CYCLES", + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "72", + "EventName": "DEA_FUNCTIONS", + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "73", + "EventName": "DEA_CYCLES", + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "74", + "EventName": "DEA_BLOCKED_FUNCTIONS", + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "75", + "EventName": "DEA_BLOCKED_CYCLES", + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "76", + "EventName": "AES_FUNCTIONS", + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "77", + "EventName": "AES_CYCLES", + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "78", + "EventName": "AES_BLOCKED_FUNCTIONS", + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, + { + "Unit": "CPU-M-CF", + "EventCode": "79", + "EventName": "AES_BLOCKED_CYCLES", + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." + }, { "Unit": "CPU-M-CF", "EventCode": "80", diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/extended.json b/tools/perf/pmu-events/arch/s390/cf_z15/extended.json index 8ac61f8f286b..9c691c391086 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/extended.json @@ -4,357 +4,357 @@ "EventCode": "128", "EventName": "L1D_RO_EXCL_WRITES", "BriefDescription": "L1D Read-only Exclusive Writes", - "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "129", "EventName": "DTLB2_WRITES", "BriefDescription": "DTLB2 Writes", - "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for what was provided for the DTLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "130", "EventName": "DTLB2_MISSES", "BriefDescription": "DTLB2 Misses", - "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle" + "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "131", "EventName": "DTLB2_HPAGE_WRITES", "BriefDescription": "DTLB2 One-Megabyte Page Writes", - "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page" + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." }, { "Unit": "CPU-M-CF", "EventCode": "132", "EventName": "DTLB2_GPAGE_WRITES", "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", - "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "133", "EventName": "L1D_L2D_SOURCED_WRITES", "BriefDescription": "L1D L2D Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." }, { "Unit": "CPU-M-CF", "EventCode": "134", "EventName": "ITLB2_WRITES", "BriefDescription": "ITLB2 Writes", - "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "ITLB2_MISSES", "BriefDescription": "ITLB2 Misses", - "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle" + "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on prior machines." }, { "Unit": "CPU-M-CF", "EventCode": "136", "EventName": "L1I_L2I_SOURCED_WRITES", "BriefDescription": "L1I L2I Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB" + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB" + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "TLB2_ENGINES_BUSY", "BriefDescription": "TLB2 Engines Busy", - "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle" + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "TX_C_TEND", "BriefDescription": "Completed TEND instructions in constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "TX_NC_TEND", "BriefDescription": "Completed TEND instructions in non-constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "143", "EventName": "L1C_TLB2_MISSES", "BriefDescription": "L1C TLB2 Misses", - "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress" + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." }, { "Unit": "CPU-M-CF", "EventCode": "144", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D On-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "149", "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "151", "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "154", "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "156", "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "157", "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "158", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO", "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "162", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "163", "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I On-Chip Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory." }, { "Unit": "CPU-M-CF", "EventCode": "164", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "165", "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "166", "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I On-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "167", "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "168", "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Cluster L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "169", "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I Off-Cluster Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory." }, { "Unit": "CPU-M-CF", "EventCode": "170", "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "171", "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "172", "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." }, { "Unit": "CPU-M-CF", "EventCode": "173", "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "174", "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "175", "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Drawer L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "224", "EventName": "BCD_DFP_EXECUTION_SLOTS", "BriefDescription": "BCD DFP Execution Slots", - "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT" + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." }, { "Unit": "CPU-M-CF", "EventCode": "225", "EventName": "VX_BCD_EXECUTION_SLOTS", "BriefDescription": "VX BCD Execution Slots", - "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG" + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG." }, { "Unit": "CPU-M-CF", "EventCode": "226", "EventName": "DECIMAL_INSTRUCTIONS", "BriefDescription": "Decimal Instructions", - "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP" + "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." }, { "Unit": "CPU-M-CF", "EventCode": "232", "EventName": "LAST_HOST_TRANSLATIONS", "BriefDescription": "Last host translation done", - "PublicDescription": "Last Host Translation done" + "PublicDescription": "Last Host Translation done." }, { "Unit": "CPU-M-CF", "EventCode": "243", "EventName": "TX_NC_TABORT", "BriefDescription": "Aborted transactions in non-constrained TX mode", - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "244", "EventName": "TX_C_TABORT_NO_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", "EventCode": "245", "EventName": "TX_C_TABORT_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", @@ -374,15 +374,15 @@ "Unit": "CPU-M-CF", "EventCode": "264", "EventName": "DFLT_CC", - "BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed", + "BriefDescription": "Increments DEFLATE CONVERSION CALL", "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed" }, { "Unit": "CPU-M-CF", "EventCode": "265", "EventName": "DFLT_CCFINISH", - "BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2", - "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2" + "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", + "PublicDescription": " Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2 complete. " }, { "Unit": "CPU-M-CF", diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json index 783de7f1aeaa..9bd20a5f47af 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json @@ -3,84 +3,84 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "34", "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", - "BriefDescription": "Problem-State L1I Directory Writes", - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "35", "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1I Penalty Cycles", - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "36", "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", - "BriefDescription": "Problem-State L1D Directory Writes", - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "37", "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1D Penalty Cycles", - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json index 3f28007d3892..a8d391ddeb8c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json +++ b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json @@ -3,112 +3,112 @@ "Unit": "CPU-M-CF", "EventCode": "64", "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "65", "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "66", "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "67", "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "68", "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "69", "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "70", "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "71", "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "72", "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "73", "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "74", "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "75", "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "76", "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "77", "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "78", "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "79", "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json index 86b29fd181cf..6ebbdbaf7951 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json @@ -4,14 +4,14 @@ "EventCode": "128", "EventName": "L1D_L2_SOURCED_WRITES", "BriefDescription": "L1D L2 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from the Level-2 cache." }, { "Unit": "CPU-M-CF", "EventCode": "129", "EventName": "L1I_L2_SOURCED_WRITES", "BriefDescription": "L1I L2 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 cache." }, { "Unit": "CPU-M-CF", @@ -32,139 +32,139 @@ "EventCode": "133", "EventName": "L2C_STORES_SENT", "BriefDescription": "L2C Stores Sent", - "PublicDescription": "Incremented by one for every store sent to Level-2 cache" + "PublicDescription": "Incremented by one for every store sent to Level-2 cache." }, { "Unit": "CPU-M-CF", "EventCode": "134", "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Book L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-3 cache." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "136", "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "L1D_RO_EXCL_WRITES", "BriefDescription": "L1D Read-only Exclusive Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "DTLB1_HPAGE_WRITES", "BriefDescription": "DTLB1 One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "L1D_LMEM_SOURCED_WRITES", "BriefDescription": "L1D Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Data Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "142", "EventName": "L1I_LMEM_SOURCED_WRITES", "BriefDescription": "L1I Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "143", "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Book L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-3 cache." }, { "Unit": "CPU-M-CF", "EventCode": "144", "EventName": "DTLB1_WRITES", "BriefDescription": "DTLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "ITLB1_WRITES", "BriefDescription": "ITLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "TLB2_CRSTE_HPAGE_WRITES", "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Chip Level-3 cache." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Chip Level-3 cache." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache" + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json index 783de7f1aeaa..9bd20a5f47af 100644 --- a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json @@ -3,84 +3,84 @@ "Unit": "CPU-M-CF", "EventCode": "0", "EventName": "CPU_CYCLES", - "BriefDescription": "CPU Cycles", - "PublicDescription": "Cycle Count" + "BriefDescription": "Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "1", "EventName": "INSTRUCTIONS", - "BriefDescription": "Instructions", - "PublicDescription": "Instruction Count" + "BriefDescription": "Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "2", "EventName": "L1I_DIR_WRITES", - "BriefDescription": "L1I Directory Writes", - "PublicDescription": "Level-1 I-Cache Directory Write Count" + "BriefDescription": "Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "3", "EventName": "L1I_PENALTY_CYCLES", - "BriefDescription": "L1I Penalty Cycles", - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." }, { "Unit": "CPU-M-CF", "EventCode": "4", "EventName": "L1D_DIR_WRITES", - "BriefDescription": "L1D Directory Writes", - "PublicDescription": "Level-1 D-Cache Directory Write Count" + "BriefDescription": "Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." }, { "Unit": "CPU-M-CF", "EventCode": "5", "EventName": "L1D_PENALTY_CYCLES", - "BriefDescription": "L1D Penalty Cycles", - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." }, { "Unit": "CPU-M-CF", "EventCode": "32", "EventName": "PROBLEM_STATE_CPU_CYCLES", - "BriefDescription": "Problem-State CPU Cycles", - "PublicDescription": "Problem-State Cycle Count" + "BriefDescription": "Problem-State Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." }, { "Unit": "CPU-M-CF", "EventCode": "33", "EventName": "PROBLEM_STATE_INSTRUCTIONS", - "BriefDescription": "Problem-State Instructions", - "PublicDescription": "Problem-State Instruction Count" + "BriefDescription": "Problem-State Instruction Count", + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "34", "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", - "BriefDescription": "Problem-State L1I Directory Writes", - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "35", "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1I Penalty Cycles", - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "36", "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", - "BriefDescription": "Problem-State L1D Directory Writes", - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." }, { "Unit": "CPU-M-CF", "EventCode": "37", "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", - "BriefDescription": "Problem-State L1D Penalty Cycles", - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json index 3f28007d3892..a8d391ddeb8c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json @@ -3,112 +3,112 @@ "Unit": "CPU-M-CF", "EventCode": "64", "EventName": "PRNG_FUNCTIONS", - "BriefDescription": "PRNG Functions", - "PublicDescription": "Total number of the PRNG functions issued by the CPU" + "BriefDescription": "PRNG Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "65", "EventName": "PRNG_CYCLES", - "BriefDescription": "PRNG Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" + "BriefDescription": "PRNG Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "66", "EventName": "PRNG_BLOCKED_FUNCTIONS", - "BriefDescription": "PRNG Blocked Functions", - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Function Count", + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "67", "EventName": "PRNG_BLOCKED_CYCLES", - "BriefDescription": "PRNG Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "PRNG Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "68", "EventName": "SHA_FUNCTIONS", - "BriefDescription": "SHA Functions", - "PublicDescription": "Total number of SHA functions issued by the CPU" + "BriefDescription": "SHA Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "69", "EventName": "SHA_CYCLES", - "BriefDescription": "SHA Cycles", - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" + "BriefDescription": "SHA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "70", "EventName": "SHA_BLOCKED_FUNCTIONS", - "BriefDescription": "SHA Blocked Functions", - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "71", "EventName": "SHA_BLOCKED_CYCLES", - "BriefDescription": "SHA Bloced Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "SHA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "72", "EventName": "DEA_FUNCTIONS", - "BriefDescription": "DEA Functions", - "PublicDescription": "Total number of the DEA functions issued by the CPU" + "BriefDescription": "DEA Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "73", "EventName": "DEA_CYCLES", - "BriefDescription": "DEA Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" + "BriefDescription": "DEA Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "74", "EventName": "DEA_BLOCKED_FUNCTIONS", - "BriefDescription": "DEA Blocked Functions", - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Function Count", + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "75", "EventName": "DEA_BLOCKED_CYCLES", - "BriefDescription": "DEA Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "DEA Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "76", "EventName": "AES_FUNCTIONS", - "BriefDescription": "AES Functions", - "PublicDescription": "Total number of AES functions issued by the CPU" + "BriefDescription": "AES Function Count", + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "77", "EventName": "AES_CYCLES", - "BriefDescription": "AES Cycles", - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" + "BriefDescription": "AES Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." }, { "Unit": "CPU-M-CF", "EventCode": "78", "EventName": "AES_BLOCKED_FUNCTIONS", - "BriefDescription": "AES Blocked Functions", - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Function Count", + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." }, { "Unit": "CPU-M-CF", "EventCode": "79", "EventName": "AES_BLOCKED_CYCLES", - "BriefDescription": "AES Blocked Cycles", - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" + "BriefDescription": "AES Blocked Cycle Count", + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json index f40cbed89418..9e765581382b 100644 --- a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json @@ -18,230 +18,230 @@ "EventCode": "130", "EventName": "L1D_L2I_SOURCED_WRITES", "BriefDescription": "L1D L2I Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache." }, { "Unit": "CPU-M-CF", "EventCode": "131", "EventName": "L1I_L2I_SOURCED_WRITES", "BriefDescription": "L1I L2I Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." }, { "Unit": "CPU-M-CF", "EventCode": "132", "EventName": "L1D_L2D_SOURCED_WRITES", "BriefDescription": "L1D L2D Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." }, { "Unit": "CPU-M-CF", "EventCode": "133", "EventName": "DTLB1_WRITES", "BriefDescription": "DTLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "135", "EventName": "L1D_LMEM_SOURCED_WRITES", "BriefDescription": "L1D Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "137", "EventName": "L1I_LMEM_SOURCED_WRITES", "BriefDescription": "L1I Local Memory Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)" + "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)." }, { "Unit": "CPU-M-CF", "EventCode": "138", "EventName": "L1D_RO_EXCL_WRITES", "BriefDescription": "L1D Read-only Exclusive Writes", - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." }, { "Unit": "CPU-M-CF", "EventCode": "139", "EventName": "DTLB1_HPAGE_WRITES", "BriefDescription": "DTLB1 One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." }, { "Unit": "CPU-M-CF", "EventCode": "140", "EventName": "ITLB1_WRITES", "BriefDescription": "ITLB1 Writes", - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." }, { "Unit": "CPU-M-CF", "EventCode": "141", "EventName": "TLB2_PTE_WRITES", "BriefDescription": "TLB2 PTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "142", "EventName": "TLB2_CRSTE_HPAGE_WRITES", "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." }, { "Unit": "CPU-M-CF", "EventCode": "143", "EventName": "TLB2_CRSTE_WRITES", "BriefDescription": "TLB2 CRSTE Writes", - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." }, { "Unit": "CPU-M-CF", "EventCode": "144", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "145", "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES", "BriefDescription": "L1D Off-Book L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1D On-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1D Off-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "149", "EventName": "TX_NC_TEND", "BriefDescription": "Completed TEND instructions in non-constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "150", "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "151", "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "152", "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV", "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "153", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I On-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "154", "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Chip L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "155", "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES", "BriefDescription": "L1I Off-Book L3 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention." }, { "Unit": "CPU-M-CF", "EventCode": "156", "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1I On-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "157", "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES", "BriefDescription": "L1I Off-Book L4 Sourced Writes", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache." }, { "Unit": "CPU-M-CF", "EventCode": "158", "EventName": "TX_C_TEND", "BriefDescription": "Completed TEND instructions in constrained TX mode", - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "159", "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "160", "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "161", "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV", "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "177", "EventName": "TX_NC_TABORT", "BriefDescription": "Aborted transactions in non-constrained TX mode", - "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode" + "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode." }, { "Unit": "CPU-M-CF", "EventCode": "178", "EventName": "TX_C_TABORT_NO_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." }, { "Unit": "CPU-M-CF", "EventCode": "179", "EventName": "TX_C_TABORT_SPECIAL", "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." } ] -- 2.36.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] perf list: Update event description for s390 machines to latest level 2022-05-30 10:56 ` [PATCH 2/2] perf list: Update event description for s390 machines to latest level Thomas Richter @ 2022-05-31 14:57 ` Ian Rogers 0 siblings, 0 replies; 5+ messages in thread From: Ian Rogers @ 2022-05-31 14:57 UTC (permalink / raw) To: Thomas Richter Cc: linux-kernel, linux-perf-users, acme, svens, gor, sumanthk, hca On Mon, May 30, 2022 at 3:57 AM Thomas Richter <tmricht@linux.ibm.com> wrote: > > Update all s390 event counter description to the latest level > as described in the documents > 1. SA23-2260-07: > "The Load-Program-Parameter and the CPU-Measurement Facilities." > released on May, 2022 > for the following counter sets: > * Basic counter set > * Crypto counter set > * MT-Diagnostic counter set > > 2. SA23-2261-07: > "The CPU-Measurement Facility Extended Counters Definition > for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" > released on April 29, 2022. > for the following counter sets: > * Extended counter set > * MT-Diagnostic counter set > > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> > Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Acked-by: Ian Rogers <irogers@google.com> Thanks, Ian > --- > .../pmu-events/arch/s390/cf_z10/basic.json | 48 ++++---- > .../pmu-events/arch/s390/cf_z10/crypto.json | 64 +++++----- > .../pmu-events/arch/s390/cf_z10/extended.json | 36 +++--- > .../pmu-events/arch/s390/cf_z13/basic.json | 48 ++++---- > .../pmu-events/arch/s390/cf_z13/crypto.json | 64 +++++----- > .../pmu-events/arch/s390/cf_z13/extended.json | 100 +++++++-------- > .../pmu-events/arch/s390/cf_z14/basic.json | 32 ++--- > .../pmu-events/arch/s390/cf_z14/crypto.json | 64 +++++----- > .../pmu-events/arch/s390/cf_z14/extended.json | 102 ++++++++-------- > .../pmu-events/arch/s390/cf_z15/basic.json | 32 ++--- > .../pmu-events/arch/s390/cf_z15/crypto.json | 114 ------------------ > .../pmu-events/arch/s390/cf_z15/crypto6.json | 112 +++++++++++++++++ > .../pmu-events/arch/s390/cf_z15/extended.json | 108 ++++++++--------- > .../pmu-events/arch/s390/cf_z196/basic.json | 48 ++++---- > .../pmu-events/arch/s390/cf_z196/crypto.json | 64 +++++----- > .../arch/s390/cf_z196/extended.json | 44 +++---- > .../pmu-events/arch/s390/cf_zec12/basic.json | 48 ++++---- > .../pmu-events/arch/s390/cf_zec12/crypto.json | 64 +++++----- > .../arch/s390/cf_zec12/extended.json | 66 +++++----- > 19 files changed, 628 insertions(+), 630 deletions(-) > delete mode 100644 tools/perf/pmu-events/arch/s390/cf_z15/crypto.json > > diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json > index 783de7f1aeaa..9bd20a5f47af 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json > @@ -3,84 +3,84 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "34", > "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", > - "BriefDescription": "Problem-State L1I Directory Writes", > - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "35", > "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1I Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "36", > "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", > - "BriefDescription": "Problem-State L1D Directory Writes", > - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "37", > "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1D Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json > index 3f28007d3892..a8d391ddeb8c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json > @@ -3,112 +3,112 @@ > "Unit": "CPU-M-CF", > "EventCode": "64", > "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "65", > "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "66", > "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "67", > "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "68", > "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "69", > "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "70", > "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "71", > "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "72", > "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "73", > "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "74", > "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "75", > "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "76", > "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "77", > "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "78", > "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "79", > "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json > index 86bd8ba9391d..bf6a9811e014 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json > @@ -4,125 +4,125 @@ > "EventCode": "128", > "EventName": "L1I_L2_SOURCED_WRITES", > "BriefDescription": "L1I L2 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "129", > "EventName": "L1D_L2_SOURCED_WRITES", > "BriefDescription": "L1D L2 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "130", > "EventName": "L1I_L3_LOCAL_WRITES", > "BriefDescription": "L1I L3 Local Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "131", > "EventName": "L1D_L3_LOCAL_WRITES", > "BriefDescription": "L1D L3 Local Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "132", > "EventName": "L1I_L3_REMOTE_WRITES", > "BriefDescription": "L1I L3 Remote Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "133", > "EventName": "L1D_L3_REMOTE_WRITES", > "BriefDescription": "L1D L3 Remote Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "134", > "EventName": "L1D_LMEM_SOURCED_WRITES", > "BriefDescription": "L1D Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "L1I_LMEM_SOURCED_WRITES", > "BriefDescription": "L1I Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "136", > "EventName": "L1D_RO_EXCL_WRITES", > "BriefDescription": "L1D Read-only Exclusive Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" > + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "L1I_CACHELINE_INVALIDATES", > "BriefDescription": "L1I Cacheline Invalidates", > - "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache" > + "PublicDescription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the same CPU as the Level-1 Instruction Cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "ITLB1_WRITES", > "BriefDescription": "ITLB1 Writes", > - "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "DTLB1_WRITES", > "BriefDescription": "DTLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "142", > "EventName": "TLB2_CRSTE_HPAGE_WRITES", > "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "ITLB1_MISSES", > "BriefDescription": "ITLB1 Misses", > - "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress" > + "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "DTLB1_MISSES", > "BriefDescription": "DTLB1 Misses", > - "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress" > + "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "L2C_STORES_SENT", > "BriefDescription": "L2C Stores Sent", > - "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache" > + "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json > index 783de7f1aeaa..9bd20a5f47af 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json > @@ -3,84 +3,84 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "34", > "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", > - "BriefDescription": "Problem-State L1I Directory Writes", > - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "35", > "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1I Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "36", > "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", > - "BriefDescription": "Problem-State L1D Directory Writes", > - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "37", > "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1D Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json > index 3f28007d3892..a8d391ddeb8c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json > @@ -3,112 +3,112 @@ > "Unit": "CPU-M-CF", > "EventCode": "64", > "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "65", > "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "66", > "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "67", > "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "68", > "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "69", > "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "70", > "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "71", > "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "72", > "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "73", > "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "74", > "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "75", > "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "76", > "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "77", > "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "78", > "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "79", > "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json > index 1a5e4f89c57e..99c1b93a7e36 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json > @@ -11,7 +11,7 @@ > "EventCode": "129", > "EventName": "DTLB1_WRITES", > "BriefDescription": "DTLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." > }, > { > "Unit": "CPU-M-CF", > @@ -25,7 +25,7 @@ > "EventCode": "131", > "EventName": "DTLB1_HPAGE_WRITES", > "BriefDescription": "DTLB1 One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." > }, > { > "Unit": "CPU-M-CF", > @@ -39,63 +39,63 @@ > "EventCode": "133", > "EventName": "L1D_L2D_SOURCED_WRITES", > "BriefDescription": "L1D L2D Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "134", > "EventName": "ITLB1_WRITES", > "BriefDescription": "ITLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "ITLB1_MISSES", > "BriefDescription": "ITLB1 Misses", > - "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress" > + "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "136", > "EventName": "L1I_L2I_SOURCED_WRITES", > "BriefDescription": "L1I L2I Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "TLB2_CRSTE_HPAGE_WRITES", > "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "TX_C_TEND", > "BriefDescription": "Completed TEND instructions in constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "TX_NC_TEND", > "BriefDescription": "Completed TEND instructions in non-constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > @@ -109,273 +109,273 @@ > "EventCode": "144", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "L1D_ONNODE_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Node L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "148", > "EventName": "L1D_ONNODE_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Node L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "149", > "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "150", > "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "151", > "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "152", > "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "153", > "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "154", > "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "155", > "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "156", > "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "157", > "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "158", > "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES", > "BriefDescription": "L1D On-Node Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "159", > "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES", > "BriefDescription": "L1D On-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "160", > "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "161", > "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "162", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "163", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "164", > "EventName": "L1I_ONNODE_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "165", > "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "166", > "EventName": "L1I_ONNODE_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Node L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "167", > "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "168", > "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "169", > "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "170", > "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "171", > "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "172", > "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "173", > "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "174", > "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "175", > "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "176", > "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES", > "BriefDescription": "L1I On-Node Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "177", > "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES", > "BriefDescription": "L1I On-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "178", > "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "179", > "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "218", > "EventName": "TX_NC_TABORT", > "BriefDescription": "Aborted transactions in non-constrained TX mode", > - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" > + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "219", > "EventName": "TX_C_TABORT_NO_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "220", > "EventName": "TX_C_TABORT_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json > index fc762e9f1d6e..1023d47028ce 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json > @@ -3,56 +3,56 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json > index 3f28007d3892..a8d391ddeb8c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json > @@ -3,112 +3,112 @@ > "Unit": "CPU-M-CF", > "EventCode": "64", > "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "65", > "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "66", > "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "67", > "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "68", > "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "69", > "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "70", > "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "71", > "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "72", > "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "73", > "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "74", > "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "75", > "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "76", > "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "77", > "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "78", > "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "79", > "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json > index 4942b20a1ea1..ad40cc4f9727 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json > @@ -4,357 +4,357 @@ > "EventCode": "128", > "EventName": "L1D_RO_EXCL_WRITES", > "BriefDescription": "L1D Read-only Exclusive Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" > + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "129", > "EventName": "DTLB2_WRITES", > "BriefDescription": "DTLB2 Writes", > - "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" > + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for what was provided for the DTLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "130", > "EventName": "DTLB2_MISSES", > "BriefDescription": "DTLB2 Misses", > - "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle" > + "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "131", > "EventName": "DTLB2_HPAGE_WRITES", > "BriefDescription": "DTLB2 One-Megabyte Page Writes", > - "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done" > + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "132", > "EventName": "DTLB2_GPAGE_WRITES", > "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", > - "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" > + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "133", > "EventName": "L1D_L2D_SOURCED_WRITES", > "BriefDescription": "L1D L2D Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "134", > "EventName": "ITLB2_WRITES", > "BriefDescription": "ITLB2 Writes", > - "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" > + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "ITLB2_MISSES", > "BriefDescription": "ITLB2 Misses", > - "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle" > + "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "136", > "EventName": "L1I_L2I_SOURCED_WRITES", > "BriefDescription": "L1I L2I Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB" > + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB" > + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "TLB2_ENGINES_BUSY", > "BriefDescription": "TLB2 Engines Busy", > - "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle" > + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "TX_C_TEND", > "BriefDescription": "Completed TEND instructions in constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "TX_NC_TEND", > "BriefDescription": "Completed TEND instructions in non-constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "143", > "EventName": "L1C_TLB2_MISSES", > "BriefDescription": "L1C TLB2 Misses", > - "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress" > + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "144", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "148", > "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D On-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "149", > "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "150", > "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "151", > "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "152", > "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "153", > "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "154", > "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "155", > "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "156", > "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "157", > "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "158", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO", > "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "162", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "163", > "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "164", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "165", > "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "166", > "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I On-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "167", > "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "168", > "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "169", > "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I Off-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "170", > "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "171", > "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "172", > "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "173", > "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "174", > "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "175", > "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "224", > "EventName": "BCD_DFP_EXECUTION_SLOTS", > "BriefDescription": "BCD DFP Execution Slots", > - "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT" > + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "225", > "EventName": "VX_BCD_EXECUTION_SLOTS", > "BriefDescription": "VX BCD Execution Slots", > - "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG" > + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "226", > "EventName": "DECIMAL_INSTRUCTIONS", > "BriefDescription": "Decimal Instructions", > - "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP" > + "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "232", > "EventName": "LAST_HOST_TRANSLATIONS", > "BriefDescription": "Last host translation done", > - "PublicDescription": "Last Host Translation done" > + "PublicDescription": "Last Host Translation done." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "243", > "EventName": "TX_NC_TABORT", > "BriefDescription": "Aborted transactions in non-constrained TX mode", > - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" > + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "244", > "EventName": "TX_C_TABORT_NO_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "245", > "EventName": "TX_C_TABORT_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/basic.json b/tools/perf/pmu-events/arch/s390/cf_z15/basic.json > index fc762e9f1d6e..1023d47028ce 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z15/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z15/basic.json > @@ -3,56 +3,56 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json > deleted file mode 100644 > index 3f28007d3892..000000000000 > --- a/tools/perf/pmu-events/arch/s390/cf_z15/crypto.json > +++ /dev/null > @@ -1,114 +0,0 @@ > -[ > - { > - "Unit": "CPU-M-CF", > - "EventCode": "64", > - "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "65", > - "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "66", > - "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "67", > - "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "68", > - "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "69", > - "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "70", > - "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "71", > - "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "72", > - "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "73", > - "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "74", > - "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "75", > - "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "76", > - "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "77", > - "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "78", > - "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - }, > - { > - "Unit": "CPU-M-CF", > - "EventCode": "79", > - "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > - } > -] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json b/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json > index ad79189050a0..8b4380b8e489 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z15/crypto6.json > @@ -1,4 +1,116 @@ > [ > + { > + "Unit": "CPU-M-CF", > + "EventCode": "64", > + "EventName": "PRNG_FUNCTIONS", > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "65", > + "EventName": "PRNG_CYCLES", > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "66", > + "EventName": "PRNG_BLOCKED_FUNCTIONS", > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "67", > + "EventName": "PRNG_BLOCKED_CYCLES", > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "68", > + "EventName": "SHA_FUNCTIONS", > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "69", > + "EventName": "SHA_CYCLES", > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "70", > + "EventName": "SHA_BLOCKED_FUNCTIONS", > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "71", > + "EventName": "SHA_BLOCKED_CYCLES", > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "72", > + "EventName": "DEA_FUNCTIONS", > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "73", > + "EventName": "DEA_CYCLES", > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "74", > + "EventName": "DEA_BLOCKED_FUNCTIONS", > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "75", > + "EventName": "DEA_BLOCKED_CYCLES", > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "76", > + "EventName": "AES_FUNCTIONS", > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "77", > + "EventName": "AES_CYCLES", > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "78", > + "EventName": "AES_BLOCKED_FUNCTIONS", > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "79", > + "EventName": "AES_BLOCKED_CYCLES", > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > { > "Unit": "CPU-M-CF", > "EventCode": "80", > diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/extended.json b/tools/perf/pmu-events/arch/s390/cf_z15/extended.json > index 8ac61f8f286b..9c691c391086 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z15/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z15/extended.json > @@ -4,357 +4,357 @@ > "EventCode": "128", > "EventName": "L1D_RO_EXCL_WRITES", > "BriefDescription": "L1D Read-only Exclusive Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" > + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "129", > "EventName": "DTLB2_WRITES", > "BriefDescription": "DTLB2 Writes", > - "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" > + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache. This is a replacement for what was provided for the DTLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "130", > "EventName": "DTLB2_MISSES", > "BriefDescription": "DTLB2 Misses", > - "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle" > + "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "131", > "EventName": "DTLB2_HPAGE_WRITES", > "BriefDescription": "DTLB2 One-Megabyte Page Writes", > - "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page" > + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "132", > "EventName": "DTLB2_GPAGE_WRITES", > "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", > - "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" > + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "133", > "EventName": "L1D_L2D_SOURCED_WRITES", > "BriefDescription": "L1D L2D Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "134", > "EventName": "ITLB2_WRITES", > "BriefDescription": "ITLB2 Writes", > - "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" > + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "ITLB2_MISSES", > "BriefDescription": "ITLB2 Misses", > - "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle" > + "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on prior machines." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "136", > "EventName": "L1I_L2I_SOURCED_WRITES", > "BriefDescription": "L1I L2I Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB" > + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB" > + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "TLB2_ENGINES_BUSY", > "BriefDescription": "TLB2 Engines Busy", > - "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle" > + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "TX_C_TEND", > "BriefDescription": "Completed TEND instructions in constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "TX_NC_TEND", > "BriefDescription": "Completed TEND instructions in non-constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "143", > "EventName": "L1C_TLB2_MISSES", > "BriefDescription": "L1C TLB2 Misses", > - "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress" > + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "144", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "148", > "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D On-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "149", > "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "150", > "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "151", > "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D Off-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "152", > "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "153", > "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "154", > "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "155", > "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "156", > "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "157", > "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "158", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO", > "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "162", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "163", > "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "164", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "165", > "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "166", > "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I On-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "167", > "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "168", > "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Cluster L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "169", > "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I Off-Cluster Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "170", > "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "171", > "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "172", > "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "173", > "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "174", > "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "175", > "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Drawer L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "224", > "EventName": "BCD_DFP_EXECUTION_SLOTS", > "BriefDescription": "BCD DFP Execution Slots", > - "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT" > + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "225", > "EventName": "VX_BCD_EXECUTION_SLOTS", > "BriefDescription": "VX BCD Execution Slots", > - "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG" > + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "226", > "EventName": "DECIMAL_INSTRUCTIONS", > "BriefDescription": "Decimal Instructions", > - "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP" > + "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "232", > "EventName": "LAST_HOST_TRANSLATIONS", > "BriefDescription": "Last host translation done", > - "PublicDescription": "Last Host Translation done" > + "PublicDescription": "Last Host Translation done." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "243", > "EventName": "TX_NC_TABORT", > "BriefDescription": "Aborted transactions in non-constrained TX mode", > - "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode" > + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "244", > "EventName": "TX_C_TABORT_NO_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "245", > "EventName": "TX_C_TABORT_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > @@ -374,15 +374,15 @@ > "Unit": "CPU-M-CF", > "EventCode": "264", > "EventName": "DFLT_CC", > - "BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed", > + "BriefDescription": "Increments DEFLATE CONVERSION CALL", > "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed" > }, > { > "Unit": "CPU-M-CF", > "EventCode": "265", > "EventName": "DFLT_CCFINISH", > - "BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2", > - "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2" > + "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", > + "PublicDescription": " Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2 complete. " > }, > { > "Unit": "CPU-M-CF", > diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json > index 783de7f1aeaa..9bd20a5f47af 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json > @@ -3,84 +3,84 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "34", > "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", > - "BriefDescription": "Problem-State L1I Directory Writes", > - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "35", > "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1I Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "36", > "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", > - "BriefDescription": "Problem-State L1D Directory Writes", > - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "37", > "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1D Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json > index 3f28007d3892..a8d391ddeb8c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json > @@ -3,112 +3,112 @@ > "Unit": "CPU-M-CF", > "EventCode": "64", > "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "65", > "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "66", > "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "67", > "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "68", > "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "69", > "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "70", > "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "71", > "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "72", > "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "73", > "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "74", > "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "75", > "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "76", > "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "77", > "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "78", > "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "79", > "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json > index 86b29fd181cf..6ebbdbaf7951 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json > @@ -4,14 +4,14 @@ > "EventCode": "128", > "EventName": "L1D_L2_SOURCED_WRITES", > "BriefDescription": "L1D L2 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from the Level-2 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "129", > "EventName": "L1I_L2_SOURCED_WRITES", > "BriefDescription": "L1I L2 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 cache." > }, > { > "Unit": "CPU-M-CF", > @@ -32,139 +32,139 @@ > "EventCode": "133", > "EventName": "L2C_STORES_SENT", > "BriefDescription": "L2C Stores Sent", > - "PublicDescription": "Incremented by one for every store sent to Level-2 cache" > + "PublicDescription": "Incremented by one for every store sent to Level-2 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "134", > "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Book L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-3 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "136", > "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "L1D_RO_EXCL_WRITES", > "BriefDescription": "L1D Read-only Exclusive Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" > + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "DTLB1_HPAGE_WRITES", > "BriefDescription": "DTLB1 One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "L1D_LMEM_SOURCED_WRITES", > "BriefDescription": "L1D Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Data Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "142", > "EventName": "L1I_LMEM_SOURCED_WRITES", > "BriefDescription": "L1I Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "143", > "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Book L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-3 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "144", > "EventName": "DTLB1_WRITES", > "BriefDescription": "DTLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "ITLB1_WRITES", > "BriefDescription": "ITLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "TLB2_CRSTE_HPAGE_WRITES", > "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "148", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "150", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Chip Level-3 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "152", > "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "153", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Chip Level-3 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "155", > "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json > index 783de7f1aeaa..9bd20a5f47af 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json > +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json > @@ -3,84 +3,84 @@ > "Unit": "CPU-M-CF", > "EventCode": "0", > "EventName": "CPU_CYCLES", > - "BriefDescription": "CPU Cycles", > - "PublicDescription": "Cycle Count" > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "1", > "EventName": "INSTRUCTIONS", > - "BriefDescription": "Instructions", > - "PublicDescription": "Instruction Count" > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "2", > "EventName": "L1I_DIR_WRITES", > - "BriefDescription": "L1I Directory Writes", > - "PublicDescription": "Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "3", > "EventName": "L1I_PENALTY_CYCLES", > - "BriefDescription": "L1I Penalty Cycles", > - "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "4", > "EventName": "L1D_DIR_WRITES", > - "BriefDescription": "L1D Directory Writes", > - "PublicDescription": "Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "5", > "EventName": "L1D_PENALTY_CYCLES", > - "BriefDescription": "L1D Penalty Cycles", > - "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "32", > "EventName": "PROBLEM_STATE_CPU_CYCLES", > - "BriefDescription": "Problem-State CPU Cycles", > - "PublicDescription": "Problem-State Cycle Count" > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "33", > "EventName": "PROBLEM_STATE_INSTRUCTIONS", > - "BriefDescription": "Problem-State Instructions", > - "PublicDescription": "Problem-State Instruction Count" > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "34", > "EventName": "PROBLEM_STATE_L1I_DIR_WRITES", > - "BriefDescription": "Problem-State L1I Directory Writes", > - "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "35", > "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1I Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count" > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "36", > "EventName": "PROBLEM_STATE_L1D_DIR_WRITES", > - "BriefDescription": "Problem-State L1D Directory Writes", > - "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "37", > "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES", > - "BriefDescription": "Problem-State L1D Penalty Cycles", > - "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count" > + "BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json > index 3f28007d3892..a8d391ddeb8c 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json > +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json > @@ -3,112 +3,112 @@ > "Unit": "CPU-M-CF", > "EventCode": "64", > "EventName": "PRNG_FUNCTIONS", > - "BriefDescription": "PRNG Functions", > - "PublicDescription": "Total number of the PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "65", > "EventName": "PRNG_CYCLES", > - "BriefDescription": "PRNG Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU" > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "66", > "EventName": "PRNG_BLOCKED_FUNCTIONS", > - "BriefDescription": "PRNG Blocked Functions", > - "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "67", > "EventName": "PRNG_BLOCKED_CYCLES", > - "BriefDescription": "PRNG Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "68", > "EventName": "SHA_FUNCTIONS", > - "BriefDescription": "SHA Functions", > - "PublicDescription": "Total number of SHA functions issued by the CPU" > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "69", > "EventName": "SHA_CYCLES", > - "BriefDescription": "SHA Cycles", > - "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU" > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "70", > "EventName": "SHA_BLOCKED_FUNCTIONS", > - "BriefDescription": "SHA Blocked Functions", > - "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "71", > "EventName": "SHA_BLOCKED_CYCLES", > - "BriefDescription": "SHA Bloced Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "72", > "EventName": "DEA_FUNCTIONS", > - "BriefDescription": "DEA Functions", > - "PublicDescription": "Total number of the DEA functions issued by the CPU" > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "73", > "EventName": "DEA_CYCLES", > - "BriefDescription": "DEA Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU" > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "74", > "EventName": "DEA_BLOCKED_FUNCTIONS", > - "BriefDescription": "DEA Blocked Functions", > - "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "75", > "EventName": "DEA_BLOCKED_CYCLES", > - "BriefDescription": "DEA Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "76", > "EventName": "AES_FUNCTIONS", > - "BriefDescription": "AES Functions", > - "PublicDescription": "Total number of AES functions issued by the CPU" > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "77", > "EventName": "AES_CYCLES", > - "BriefDescription": "AES Cycles", > - "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU" > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "78", > "EventName": "AES_BLOCKED_FUNCTIONS", > - "BriefDescription": "AES Blocked Functions", > - "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "79", > "EventName": "AES_BLOCKED_CYCLES", > - "BriefDescription": "AES Blocked Cycles", > - "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU" > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > } > ] > diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json > index f40cbed89418..9e765581382b 100644 > --- a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json > +++ b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json > @@ -18,230 +18,230 @@ > "EventCode": "130", > "EventName": "L1D_L2I_SOURCED_WRITES", > "BriefDescription": "L1D L2I Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "131", > "EventName": "L1I_L2I_SOURCED_WRITES", > "BriefDescription": "L1I L2I Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "132", > "EventName": "L1D_L2D_SOURCED_WRITES", > "BriefDescription": "L1D L2D Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "133", > "EventName": "DTLB1_WRITES", > "BriefDescription": "DTLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "135", > "EventName": "L1D_LMEM_SOURCED_WRITES", > "BriefDescription": "L1D Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "137", > "EventName": "L1I_LMEM_SOURCED_WRITES", > "BriefDescription": "L1I Local Memory Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)" > + "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "138", > "EventName": "L1D_RO_EXCL_WRITES", > "BriefDescription": "L1D Read-only Exclusive Writes", > - "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line" > + "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "139", > "EventName": "DTLB1_HPAGE_WRITES", > "BriefDescription": "DTLB1 One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page" > + "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "140", > "EventName": "ITLB1_WRITES", > "BriefDescription": "ITLB1 Writes", > - "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer" > + "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "141", > "EventName": "TLB2_PTE_WRITES", > "BriefDescription": "TLB2 PTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "142", > "EventName": "TLB2_CRSTE_HPAGE_WRITES", > "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "143", > "EventName": "TLB2_CRSTE_WRITES", > "BriefDescription": "TLB2 CRSTE Writes", > - "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays" > + "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "144", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "145", > "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "146", > "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES", > "BriefDescription": "L1D Off-Book L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "147", > "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1D On-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "148", > "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1D Off-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "149", > "EventName": "TX_NC_TEND", > "BriefDescription": "Completed TEND instructions in non-constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "150", > "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "151", > "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "152", > "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "153", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I On-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "154", > "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Chip L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "155", > "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES", > "BriefDescription": "L1I Off-Book L3 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "156", > "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1I On-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "157", > "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES", > "BriefDescription": "L1I Off-Book L4 Sourced Writes", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "158", > "EventName": "TX_C_TEND", > "BriefDescription": "Completed TEND instructions in constrained TX mode", > - "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode" > + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "159", > "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "160", > "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "161", > "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV", > "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention", > - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention" > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "177", > "EventName": "TX_NC_TABORT", > "BriefDescription": "Aborted transactions in non-constrained TX mode", > - "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode" > + "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "178", > "EventName": "TX_C_TABORT_NO_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." > }, > { > "Unit": "CPU-M-CF", > "EventCode": "179", > "EventName": "TX_C_TABORT_SPECIAL", > "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", > - "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete" > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." > } > ] > -- > 2.36.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] perf list: Add IBM z16 event description for s390 2022-05-30 10:56 [PATCH 1/2] perf list: Add IBM z16 event description for s390 Thomas Richter 2022-05-30 10:56 ` [PATCH 2/2] perf list: Update event description for s390 machines to latest level Thomas Richter @ 2022-05-31 14:56 ` Ian Rogers 2022-06-03 19:36 ` Arnaldo Carvalho de Melo 1 sibling, 1 reply; 5+ messages in thread From: Ian Rogers @ 2022-05-31 14:56 UTC (permalink / raw) To: Thomas Richter Cc: linux-kernel, linux-perf-users, acme, svens, gor, sumanthk, hca On Mon, May 30, 2022 at 3:57 AM Thomas Richter <tmricht@linux.ibm.com> wrote: > > Update IBM z16 counter description using document SA23-2260-07: > "The Load-Program-Parameter and the CPU-Measurement Facilities" > released in May, 2022, to include counter definitions for IBM z16 > counter sets: > * Basic counter set > * Problem/user counter set > * Crypto counter set > > Use document SA23-2261-07: > "The CPU-Measurement Facility Extended Counters Definition > for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" > released on April 29, 2022 to include counter definitions for IBM z16 > * Extended counter set > * MT-Diagnostic counter set > > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> > Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Acked-by: Ian Rogers <irogers@google.com> Thanks, Ian > --- > .../pmu-events/arch/s390/cf_z16/basic.json | 58 +++ > .../pmu-events/arch/s390/cf_z16/crypto6.json | 142 +++++ > .../pmu-events/arch/s390/cf_z16/extended.json | 492 ++++++++++++++++++ > .../arch/s390/cf_z16/transaction.json | 7 + > tools/perf/pmu-events/arch/s390/mapfile.csv | 1 + > 5 files changed, 700 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/basic.json > create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json > create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/extended.json > create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/basic.json b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json > new file mode 100644 > index 000000000000..1023d47028ce > --- /dev/null > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json > @@ -0,0 +1,58 @@ > +[ > + { > + "Unit": "CPU-M-CF", > + "EventCode": "0", > + "EventName": "CPU_CYCLES", > + "BriefDescription": "Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "1", > + "EventName": "INSTRUCTIONS", > + "BriefDescription": "Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "2", > + "EventName": "L1I_DIR_WRITES", > + "BriefDescription": "Level-1 I-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "3", > + "EventName": "L1I_PENALTY_CYCLES", > + "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "4", > + "EventName": "L1D_DIR_WRITES", > + "BriefDescription": "Level-1 D-Cache Directory Write Count", > + "PublicDescription": "This counter counts the total number of level-1 data-cache directory writes." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "5", > + "EventName": "L1D_PENALTY_CYCLES", > + "BriefDescription": "Level-1 D-Cache Penalty Cycle Count", > + "PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "32", > + "EventName": "PROBLEM_STATE_CPU_CYCLES", > + "BriefDescription": "Problem-State Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "33", > + "EventName": "PROBLEM_STATE_INSTRUCTIONS", > + "BriefDescription": "Problem-State Instruction Count", > + "PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state." > + } > +] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json > new file mode 100644 > index 000000000000..8b4380b8e489 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json > @@ -0,0 +1,142 @@ > +[ > + { > + "Unit": "CPU-M-CF", > + "EventCode": "64", > + "EventName": "PRNG_FUNCTIONS", > + "BriefDescription": "PRNG Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "65", > + "EventName": "PRNG_CYCLES", > + "BriefDescription": "PRNG Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "66", > + "EventName": "PRNG_BLOCKED_FUNCTIONS", > + "BriefDescription": "PRNG Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "67", > + "EventName": "PRNG_BLOCKED_CYCLES", > + "BriefDescription": "PRNG Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "68", > + "EventName": "SHA_FUNCTIONS", > + "BriefDescription": "SHA Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "69", > + "EventName": "SHA_CYCLES", > + "BriefDescription": "SHA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "70", > + "EventName": "SHA_BLOCKED_FUNCTIONS", > + "BriefDescription": "SHA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "71", > + "EventName": "SHA_BLOCKED_CYCLES", > + "BriefDescription": "SHA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "72", > + "EventName": "DEA_FUNCTIONS", > + "BriefDescription": "DEA Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "73", > + "EventName": "DEA_CYCLES", > + "BriefDescription": "DEA Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "74", > + "EventName": "DEA_BLOCKED_FUNCTIONS", > + "BriefDescription": "DEA Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "75", > + "EventName": "DEA_BLOCKED_CYCLES", > + "BriefDescription": "DEA Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "76", > + "EventName": "AES_FUNCTIONS", > + "BriefDescription": "AES Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "77", > + "EventName": "AES_CYCLES", > + "BriefDescription": "AES Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "78", > + "EventName": "AES_BLOCKED_FUNCTIONS", > + "BriefDescription": "AES Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "79", > + "EventName": "AES_BLOCKED_CYCLES", > + "BriefDescription": "AES Blocked Cycle Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "80", > + "EventName": "ECC_FUNCTION_COUNT", > + "BriefDescription": "ECC Function Count", > + "PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "81", > + "EventName": "ECC_CYCLES_COUNT", > + "BriefDescription": "ECC Cycles Count", > + "PublicDescription": "This counter counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cryptography (ECC) functions issued by the CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "82", > + "EventName": "ECC_BLOCKED_FUNCTION_COUNT", > + "BriefDescription": "Ecc Blocked Function Count", > + "PublicDescription": "This counter counts the total number of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issued by another CPU." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "83", > + "EventName": "ECC_BLOCKED_CYCLES_COUNT", > + "BriefDescription": "ECC Blocked Cycles Count", > + "PublicDescription": "This counter counts the total number of CPU cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU." > + } > +] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json > new file mode 100644 > index 000000000000..c306190fc06f > --- /dev/null > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json > @@ -0,0 +1,492 @@ > +[ > + { > + "Unit": "CPU-M-CF", > + "EventCode": "128", > + "EventName": "L1D_RO_EXCL_WRITES", > + "BriefDescription": "L1D Read-only Exclusive Writes", > + "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "129", > + "EventName": "DTLB2_WRITES", > + "BriefDescription": "DTLB2 Writes", > + "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "130", > + "EventName": "DTLB2_MISSES", > + "BriefDescription": "DTLB2 Misses", > + "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "131", > + "EventName": "CRSTE_1MB_WRITES", > + "BriefDescription": "One Megabyte CRSTE writes", > + "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "132", > + "EventName": "DTLB2_GPAGE_WRITES", > + "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", > + "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "134", > + "EventName": "ITLB2_WRITES", > + "BriefDescription": "ITLB2 Writes", > + "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "135", > + "EventName": "ITLB2_MISSES", > + "BriefDescription": "ITLB2 Misses", > + "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "137", > + "EventName": "TLB2_PTE_WRITES", > + "BriefDescription": "TLB2 Page Table Entry Writes", > + "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "138", > + "EventName": "TLB2_CRSTE_WRITES", > + "BriefDescription": "TLB2 Combined Region and Segment Entry Writes", > + "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "139", > + "EventName": "TLB2_ENGINES_BUSY", > + "BriefDescription": "TLB2 Engines Busy", > + "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "140", > + "EventName": "TX_C_TEND", > + "BriefDescription": "Completed TEND instructions in constrained TX mode", > + "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "141", > + "EventName": "TX_NC_TEND", > + "BriefDescription": "Completed TEND instructions in non-constrained TX mode", > + "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "143", > + "EventName": "L1C_TLB2_MISSES", > + "BriefDescription": "L1C TLB2 Misses", > + "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "145", > + "EventName": "DCW_REQ", > + "BriefDescription": "Directory Write Level 1 Data Cache from Cache", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "146", > + "EventName": "DCW_REQ_IV", > + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "147", > + "EventName": "DCW_REQ_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "148", > + "EventName": "DCW_REQ_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "149", > + "EventName": "DCW_ON_CHIP", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "150", > + "EventName": "DCW_ON_CHIP_IV", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "151", > + "EventName": "DCW_ON_CHIP_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "152", > + "EventName": "DCW_ON_CHIP_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "153", > + "EventName": "DCW_ON_MODULE", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "154", > + "EventName": "DCW_ON_DRAWER", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "155", > + "EventName": "DCW_OFF_DRAWER", > + "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "156", > + "EventName": "DCW_ON_CHIP_MEMORY", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "157", > + "EventName": "DCW_ON_MODULE_MEMORY", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "158", > + "EventName": "DCW_ON_DRAWER_MEMORY", > + "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "159", > + "EventName": "DCW_OFF_DRAWER_MEMORY", > + "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory", > + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "160", > + "EventName": "IDCW_ON_MODULE_IV", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "161", > + "EventName": "IDCW_ON_MODULE_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "162", > + "EventName": "IDCW_ON_MODULE_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "163", > + "EventName": "IDCW_ON_DRAWER_IV", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "164", > + "EventName": "IDCW_ON_DRAWER_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "165", > + "EventName": "IDCW_ON_DRAWER_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "166", > + "EventName": "IDCW_OFF_DRAWER_IV", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "167", > + "EventName": "IDCW_OFF_DRAWER_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "168", > + "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit", > + "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "169", > + "EventName": "ICW_REQ", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "170", > + "EventName": "ICW_REQ_IV", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "171", > + "EventName": "ICW_REQ_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "172", > + "EventName": "ICW_REQ_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "173", > + "EventName": "ICW_ON_CHIP", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "174", > + "EventName": "ICW_ON_CHIP_IV", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "175", > + "EventName": "ICW_ON_CHIP_CHIP_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "176", > + "EventName": "ICW_ON_CHIP_DRAWER_HIT", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "177", > + "EventName": "ICW_ON_MODULE", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "178", > + "EventName": "ICW_ON_DRAWER", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "179", > + "EventName": "ICW_OFF_DRAWER", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "180", > + "EventName": "ICW_ON_CHIP_MEMORY", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "181", > + "EventName": "ICW_ON_MODULE_MEMORY", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "182", > + "EventName": "ICW_ON_DRAWER_MEMORY", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "183", > + "EventName": "ICW_OFF_DRAWER_MEMORY", > + "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory", > + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "224", > + "EventName": "BCD_DFP_EXECUTION_SLOTS", > + "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions", > + "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "225", > + "EventName": "VX_BCD_EXECUTION_SLOTS", > + "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions", > + "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "226", > + "EventName": "DECIMAL_INSTRUCTIONS", > + "BriefDescription": "Decimal instruction dispatched", > + "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "232", > + "EventName": "LAST_HOST_TRANSLATIONS", > + "BriefDescription": "Last host translation done", > + "PublicDescription": "Last Host Translation done" > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "244", > + "EventName": "TX_NC_TABORT", > + "BriefDescription": "Aborted transactions in unconstrained TX mode", > + "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "245", > + "EventName": "TX_C_TABORT_NO_SPECIAL", > + "BriefDescription": "Aborted transactions in constrained TX mode", > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "246", > + "EventName": "TX_C_TABORT_SPECIAL", > + "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic", > + "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "248", > + "EventName": "DFLT_ACCESS", > + "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit", > + "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit" > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "253", > + "EventName": "DFLT_CYCLES", > + "BriefDescription": "Cycles CPU is using Deflate unit", > + "PublicDescription": "Cycles CPU is using Deflate unit" > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "256", > + "EventName": "SORTL", > + "BriefDescription": "Count SORTL instructions", > + "PublicDescription": "Increments by one for every SORT LISTS instruction executed." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "265", > + "EventName": "DFLT_CC", > + "BriefDescription": "Increments DEFLATE CONVERSION CALL", > + "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "266", > + "EventName": "DFLT_CCFINISH", > + "BriefDescription": "Increments completed DEFLATE CONVERSION CALL", > + "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "267", > + "EventName": "NNPA_INVOCATIONS", > + "BriefDescription": "NNPA Total invocations", > + "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "268", > + "EventName": "NNPA_COMPLETIONS", > + "BriefDescription": "NNPA Total completions", > + "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "269", > + "EventName": "NNPA_WAIT_LOCK", > + "BriefDescription": "Cycles spent obtaining NNPA lock", > + "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "270", > + "EventName": "NNPA_HOLD_LOCK", > + "BriefDescription": "Cycles spent holding NNPA lock", > + "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI." > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "448", > + "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE", > + "BriefDescription": "Cycle count with one thread active", > + "PublicDescription": "Cycle count with one thread active" > + }, > + { > + "Unit": "CPU-M-CF", > + "EventCode": "449", > + "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE", > + "BriefDescription": "Cycle count with two threads active", > + "PublicDescription": "Cycle count with two threads active" > + } > +] > diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > new file mode 100644 > index 000000000000..1a0034f79f73 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json > @@ -0,0 +1,7 @@ > +[ > + { > + "BriefDescription": "Transaction count", > + "MetricName": "transaction", > + "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" > + } > +] > diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv > index 61641a3480e0..a918e1af77a5 100644 > --- a/tools/perf/pmu-events/arch/s390/mapfile.csv > +++ b/tools/perf/pmu-events/arch/s390/mapfile.csv > @@ -5,3 +5,4 @@ Family-model,Version,Filename,EventType > ^IBM.296[45].*[13]\.[1-5].[[:xdigit:]]+$,1,cf_z13,core > ^IBM.390[67].*[13]\.[1-5].[[:xdigit:]]+$,3,cf_z14,core > ^IBM.856[12].*3\.6.[[:xdigit:]]+$,3,cf_z15,core > +^IBM.393[12].*3\.7.[[:xdigit:]]+$,3,cf_z16,core > -- > 2.36.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] perf list: Add IBM z16 event description for s390 2022-05-31 14:56 ` [PATCH 1/2] perf list: Add IBM z16 event description for s390 Ian Rogers @ 2022-06-03 19:36 ` Arnaldo Carvalho de Melo 0 siblings, 0 replies; 5+ messages in thread From: Arnaldo Carvalho de Melo @ 2022-06-03 19:36 UTC (permalink / raw) To: Ian Rogers Cc: Thomas Richter, linux-kernel, linux-perf-users, svens, gor, sumanthk, hca Em Tue, May 31, 2022 at 07:56:04AM -0700, Ian Rogers escreveu: > On Mon, May 30, 2022 at 3:57 AM Thomas Richter <tmricht@linux.ibm.com> wrote: > > > > Update IBM z16 counter description using document SA23-2260-07: > > "The Load-Program-Parameter and the CPU-Measurement Facilities" > > released in May, 2022, to include counter definitions for IBM z16 > > counter sets: > > * Basic counter set > > * Problem/user counter set > > * Crypto counter set > > > > Use document SA23-2261-07: > > "The CPU-Measurement Facility Extended Counters Definition > > for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16" > > released on April 29, 2022 to include counter definitions for IBM z16 > > * Extended counter set > > * MT-Diagnostic counter set > > > > Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> > > Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> > > Acked-by: Ian Rogers <irogers@google.com> Thanks, applied the series. - Arnaldo ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-06-03 19:36 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-05-30 10:56 [PATCH 1/2] perf list: Add IBM z16 event description for s390 Thomas Richter 2022-05-30 10:56 ` [PATCH 2/2] perf list: Update event description for s390 machines to latest level Thomas Richter 2022-05-31 14:57 ` Ian Rogers 2022-05-31 14:56 ` [PATCH 1/2] perf list: Add IBM z16 event description for s390 Ian Rogers 2022-06-03 19:36 ` Arnaldo Carvalho de Melo
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