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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id i14-20020a056830402e00b0060b128b935csm1807450ots.39.2022.06.24.10.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jun 2022 10:06:03 -0700 (PDT) Date: Fri, 24 Jun 2022 10:08:05 -0700 From: Bjorn Andersson To: Taniya Das Cc: Stephen Boyd , Michael Turquette ? , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 1/4] clk: qcom: sc7280: Update clk_init_data to const for GCC Message-ID: References: <20220202183528.3911-1-tdas@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220202183528.3911-1-tdas@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 02 Feb 10:35 PST 2022, Taniya Das wrote: > Update clk_init_data to const and also use index instead of fw_name for > global clock controller. > > Fixes: a3cc092196ef6 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") > Signed-off-by: Taniya Das Hi Taniya, I'm not able to find a new revision of this series in the inbox, could you please respin it? > --- > drivers/clk/qcom/gcc-sc7280.c | 362 +++++++++++++++++----------------- > 1 file changed, 181 insertions(+), 181 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c > index 423627d49719..ccecd3d8a6d9 100644 > --- a/drivers/clk/qcom/gcc-sc7280.c > +++ b/drivers/clk/qcom/gcc-sc7280.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. > + * Copyright (c) 2020-2022, The Linux Foundation. All rights reserved. > */ > > #include > @@ -45,10 +45,10 @@ static struct clk_alpha_pll gcc_gpll0 = { > .clkr = { > .enable_reg = 0x52010, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data){ > + .hw.init = &(const struct clk_init_data){ And while doing so, please split this into one patch adding the const... > .name = "gcc_gpll0", > .parent_data = &(const struct clk_parent_data){ > - .fw_name = "bi_tcxo", > + .index = 0, and a separate patch changing fw_name to index. If there are regressions we want to be able to bisect it down to the right one. Also, please add a define for BI_TCXO, instead of having a comment in most places - like I did in gcc-sc8280xp.c (but as we have existing dts I don't think it's wise to replace all fw_name entries with .index).. Thanks, Bjorn