From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11F46C43334 for ; Mon, 27 Jun 2022 17:38:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235743AbiF0Rio (ORCPT ); Mon, 27 Jun 2022 13:38:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230102AbiF0Rim (ORCPT ); Mon, 27 Jun 2022 13:38:42 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77C87BC26; Mon, 27 Jun 2022 10:38:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id DC086CE1C11; Mon, 27 Jun 2022 17:38:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 68482C3411D; Mon, 27 Jun 2022 17:38:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656351518; bh=hfCfNTzc7JZtxou2jxZhmy+oXmDlCgxHOD/5k/M2B+g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YE5NQe9CzyTAASVfUPLi4dW00FrNxSGcSXhdSR3rD3D5qUqx2B+1/+D6QgmXrmJXC pQb7cpX8LXO0qZUjXDGFC/wV79fO/NFT30sUo/IBfN500jGLjDrvPDxu8sexMFWF1Q pTZ/nJs+3kUizBXrP37ZP19MKAGPFzc8zQJVo6vpqpu3pOERX37n2Iw2JlZ5WW8ICc +i4W2OyNDS81WrzRse0jcYFQnucpcqWpp9HaY0V/Rzs1oqU0S2WmZgf1NqvXxSAcrW gJBUNQpFAFP0kfj66X6H6fhwf5yApDbuxnRhlQJr620bzGtV+TksKiHLHSTVuyZAuk OxW1QVJzvyqqA== Date: Mon, 27 Jun 2022 23:08:33 +0530 From: Vinod Koul To: haijie Cc: "Wangzhou (B)" , "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 2/8] dmaengine: hisilicon: Fix CQ head update Message-ID: References: <20220625074422.3479591-1-haijie1@huawei.com> <20220625074422.3479591-3-haijie1@huawei.com> <494c689c9141429caae0285a9e778c3b@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <494c689c9141429caae0285a9e778c3b@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27-06-22, 07:01, haijie wrote: > Hi, Vinod, > > This happens bacause I rearranged this patch without checking, it will be corrected in v2. Please _do_ _not_ top post and reply inline to the queries. Otherwise it is very difficult to understand... > > Thanks. > > -----Original Message----- > From: Vinod Koul [mailto:vkoul@kernel.org] > Sent: Monday, June 27, 2022 2:13 PM > To: haijie > Cc: Wangzhou (B) ; dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/8] dmaengine: hisilicon: Fix CQ head update > > On 25-06-22, 15:44, Jie Hai wrote: > > After completion of data transfer of one or multiple descriptors, the > > completion status and the current head pointer to submission queue are > > written into the CQ and interrupt can be generated to inform the > > software. In interrupt process CQ is read and cq_head is updated. > > > > hisi_dma_irq updates cq_head only when the completion status is > > success. When an abnormal interrupt reports, cq_head will not update > > which will cause subsequent interrupt processes read the error CQ and > > never report the correct status. > > > > This patch updates cq_head whenever CQ is accessed. > > > > Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine > > support") > > > > No need for blank line > > Signed-off-by: Jie Hai > > --- > > drivers/dma/hisi_dma.c | 9 ++++----- > > 1 file changed, 4 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c index > > 98bc488893cc..0a0f8a4d168a 100644 > > --- a/drivers/dma/hisi_dma.c > > +++ b/drivers/dma/hisi_dma.c > > @@ -436,12 +436,11 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) > > desc = chan->desc; > > cqe = chan->cq + chan->cq_head; > > if (desc) { > > + chan->cq_head = (chan->cq_head + 1) % > > + hdma_dev->chan_depth; > > + hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, > > q_base? > > -- > ~Vinod -- ~Vinod