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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id k18-20020a056870819200b0010c5005d427sm3998996oae.33.2022.07.11.19.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 19:29:29 -0700 (PDT) Date: Mon, 11 Jul 2022 19:31:56 -0700 From: Bjorn Andersson To: Manivannan Sadhasivam Cc: Andy Gross , Konrad Dybcio , Johan Hovold , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: qcom: sc8280xp: Add lost ranges for timer Message-ID: References: <20220707160858.3178771-1-bjorn.andersson@linaro.org> <20220709065915.GG5063@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220709065915.GG5063@thinkpad> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 08 Jul 23:59 PDT 2022, Manivannan Sadhasivam wrote: > On Thu, Jul 07, 2022 at 09:08:58AM -0700, Bjorn Andersson wrote: > > The timer node needs ranges specified to map the 1-cell children to the > > 2-cell address range used in /soc. This addition never made it into the > > patch that was posted and merged, so add it now. > > > > Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") > > Signed-off-by: Bjorn Andersson > > --- > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > index 2bdb42c88311..37a4cd6f85b6 100644 > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > > @@ -1667,6 +1667,7 @@ timer@17c20000 { > > reg = <0x0 0x17c20000 0x0 0x1000>; > > #address-cells = <1>; > > #size-cells = <1>; > > + ranges = <0 0 0 0x20000000>; > > Even though this looks correct, I'm wondering why other SoCs are defining the > child addresses in 2 cells. I don't think the timer frames can go beyond 32bit > address space. Should we fix them too? > Neither addresses nor sizes used for mmio need more than 32 bits, but ranges and dma-ranges are expressed in #size-cells. So unless these cells are 2 there's no way for us to express the fact that (most of) our busses uses 36 address bits. And we need to be able to do this, because the SMMU on multiple platforms claims that the bus is 40 address bits, so we end up running into issues with the upper 4 bits of IOVAs being truncated. Regards, Bjorn > But for this patch, > > Reviewed-by: Manivannan Sadhasivam > > Thanks, > Mani > > > > > frame@17c21000 { > > frame-number = <0>; > > -- > > 2.35.1 > > > > -- > ??????????????????????????? ????????????????????????