* [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array
@ 2022-07-12 21:03 Prashant Malani
2022-07-12 21:03 ` [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes Prashant Malani
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Prashant Malani @ 2022-07-12 21:03 UTC (permalink / raw)
To: linux-kernel, chrome-platform
Cc: bleung, heikki.krogerus, Prashant Malani, Guenter Roeck
Rename "p_altmode" to "port_altmode" which is a less ambiguous name for
the port_altmode struct array.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
---
drivers/platform/chrome/cros_ec_typec.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index d6088ba447af..b9848e80f372 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -60,8 +60,7 @@ struct cros_typec_port {
uint8_t mux_flags;
uint8_t role;
- /* Port alt modes. */
- struct typec_altmode p_altmode[CROS_EC_ALTMODE_MAX];
+ struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX];
/* Flag indicating that PD partner discovery data parsing is completed. */
bool sop_disc_done;
@@ -282,16 +281,16 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec,
struct cros_typec_port *port = typec->ports[port_num];
/* All PD capable CrOS devices are assumed to support DP altmode. */
- port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
- port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
+ port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
+ port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
/*
* Register TBT compatibility alt mode. The EC will not enter the mode
* if it doesn't support it, so it's safe to register it unconditionally
* here for now.
*/
- port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
- port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
+ port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
+ port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
port->state.alt = NULL;
port->state.mode = TYPEC_STATE_USB;
@@ -431,7 +430,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec,
data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE;
if (!port->state.alt) {
- port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT];
+ port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT];
ret = cros_typec_usb_safe_state(port);
if (ret)
return ret;
@@ -473,7 +472,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec,
/* Configuration VDO. */
dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode);
if (!port->state.alt) {
- port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_DP];
+ port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP];
ret = cros_typec_usb_safe_state(port);
if (ret)
return ret;
--
2.37.0.144.g8ac04bfd2-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes 2022-07-12 21:03 [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Prashant Malani @ 2022-07-12 21:03 ` Prashant Malani 2022-07-18 8:38 ` Heikki Krogerus 2022-07-18 8:37 ` [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Heikki Krogerus ` (2 subsequent siblings) 3 siblings, 1 reply; 6+ messages in thread From: Prashant Malani @ 2022-07-12 21:03 UTC (permalink / raw) To: linux-kernel, chrome-platform Cc: bleung, heikki.krogerus, Prashant Malani, Guenter Roeck Instead of using manually managed altmode structs, register the port's altmodes with the Type-C framework. This facilitates matching them to partner altmodes later. Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Prashant Malani <pmalani@chromium.org> --- drivers/platform/chrome/cros_ec_typec.c | 51 +++++++++++++++++++------ 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index b9848e80f372..e67cccb9ac78 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -25,6 +25,8 @@ #define DRV_NAME "cros-ec-typec" +#define DP_PORT_VDO (BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASSIGN_D) | DP_CAP_DFP_D) + /* Supported alt modes. */ enum { CROS_EC_ALTMODE_DP = 0, @@ -60,7 +62,7 @@ struct cros_typec_port { uint8_t mux_flags; uint8_t role; - struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX]; + struct typec_altmode *port_altmode[CROS_EC_ALTMODE_MAX]; /* Flag indicating that PD partner discovery data parsing is completed. */ bool sop_disc_done; @@ -253,6 +255,14 @@ static void cros_typec_remove_cable(struct cros_typec_data *typec, port->sop_prime_disc_done = false; } +static void cros_typec_unregister_port_altmodes(struct cros_typec_port *port) +{ + int i; + + for (i = 0; i < CROS_EC_ALTMODE_MAX; i++) + typec_unregister_altmode(port->port_altmode[i]); +} + static void cros_unregister_ports(struct cros_typec_data *typec) { int i; @@ -267,34 +277,49 @@ static void cros_unregister_ports(struct cros_typec_data *typec) usb_role_switch_put(typec->ports[i]->role_sw); typec_switch_put(typec->ports[i]->ori_sw); typec_mux_put(typec->ports[i]->mux); + cros_typec_unregister_port_altmodes(typec->ports[i]); typec_unregister_port(typec->ports[i]->port); } } /* - * Fake the alt mode structs until we actually start registering Type C port - * and partner alt modes. + * Register port alt modes with known values till we start retrieving + * port capabilities from the EC. */ -static void cros_typec_register_port_altmodes(struct cros_typec_data *typec, +static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, int port_num) { struct cros_typec_port *port = typec->ports[port_num]; + struct typec_altmode_desc desc; + struct typec_altmode *amode; /* All PD capable CrOS devices are assumed to support DP altmode. */ - port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; - port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; + desc.svid = USB_TYPEC_DP_SID, + desc.mode = USB_TYPEC_DP_MODE, + desc.vdo = DP_PORT_VDO, + amode = typec_port_register_altmode(port->port, &desc); + if (IS_ERR(amode)) + return PTR_ERR(amode); + port->port_altmode[CROS_EC_ALTMODE_DP] = amode; /* * Register TBT compatibility alt mode. The EC will not enter the mode * if it doesn't support it, so it's safe to register it unconditionally * here for now. */ - port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; - port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; + memset(&desc, 0, sizeof(desc)); + desc.svid = USB_TYPEC_TBT_SID, + desc.mode = TYPEC_ANY_MODE, + amode = typec_port_register_altmode(port->port, &desc); + if (IS_ERR(amode)) + return PTR_ERR(amode); + port->port_altmode[CROS_EC_ALTMODE_TBT] = amode; port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; port->state.data = NULL; + + return 0; } static int cros_typec_init_ports(struct cros_typec_data *typec) @@ -361,7 +386,11 @@ static int cros_typec_init_ports(struct cros_typec_data *typec) dev_dbg(dev, "No switch control for port %d\n", port_num); - cros_typec_register_port_altmodes(typec, port_num); + ret = cros_typec_register_port_altmodes(typec, port_num); + if (ret) { + dev_err(dev, "Failed to register port altmodes\n"); + goto unregister_ports; + } cros_port->disc_data = devm_kzalloc(dev, EC_PROTO2_MAX_RESPONSE_SIZE, GFP_KERNEL); if (!cros_port->disc_data) { @@ -430,7 +459,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec, data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE; if (!port->state.alt) { - port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT]; + port->state.alt = port->port_altmode[CROS_EC_ALTMODE_TBT]; ret = cros_typec_usb_safe_state(port); if (ret) return ret; @@ -472,7 +501,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, /* Configuration VDO. */ dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode); if (!port->state.alt) { - port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP]; + port->state.alt = port->port_altmode[CROS_EC_ALTMODE_DP]; ret = cros_typec_usb_safe_state(port); if (ret) return ret; -- 2.37.0.144.g8ac04bfd2-goog ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes 2022-07-12 21:03 ` [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes Prashant Malani @ 2022-07-18 8:38 ` Heikki Krogerus 0 siblings, 0 replies; 6+ messages in thread From: Heikki Krogerus @ 2022-07-18 8:38 UTC (permalink / raw) To: Prashant Malani; +Cc: linux-kernel, chrome-platform, bleung, Guenter Roeck On Tue, Jul 12, 2022 at 09:03:18PM +0000, Prashant Malani wrote: > Instead of using manually managed altmode structs, register the port's > altmodes with the Type-C framework. This facilitates matching them to > partner altmodes later. > > Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> > Signed-off-by: Prashant Malani <pmalani@chromium.org> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> > --- > drivers/platform/chrome/cros_ec_typec.c | 51 +++++++++++++++++++------ > 1 file changed, 40 insertions(+), 11 deletions(-) > > diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c > index b9848e80f372..e67cccb9ac78 100644 > --- a/drivers/platform/chrome/cros_ec_typec.c > +++ b/drivers/platform/chrome/cros_ec_typec.c > @@ -25,6 +25,8 @@ > > #define DRV_NAME "cros-ec-typec" > > +#define DP_PORT_VDO (BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASSIGN_D) | DP_CAP_DFP_D) > + > /* Supported alt modes. */ > enum { > CROS_EC_ALTMODE_DP = 0, > @@ -60,7 +62,7 @@ struct cros_typec_port { > uint8_t mux_flags; > uint8_t role; > > - struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX]; > + struct typec_altmode *port_altmode[CROS_EC_ALTMODE_MAX]; > > /* Flag indicating that PD partner discovery data parsing is completed. */ > bool sop_disc_done; > @@ -253,6 +255,14 @@ static void cros_typec_remove_cable(struct cros_typec_data *typec, > port->sop_prime_disc_done = false; > } > > +static void cros_typec_unregister_port_altmodes(struct cros_typec_port *port) > +{ > + int i; > + > + for (i = 0; i < CROS_EC_ALTMODE_MAX; i++) > + typec_unregister_altmode(port->port_altmode[i]); > +} > + > static void cros_unregister_ports(struct cros_typec_data *typec) > { > int i; > @@ -267,34 +277,49 @@ static void cros_unregister_ports(struct cros_typec_data *typec) > usb_role_switch_put(typec->ports[i]->role_sw); > typec_switch_put(typec->ports[i]->ori_sw); > typec_mux_put(typec->ports[i]->mux); > + cros_typec_unregister_port_altmodes(typec->ports[i]); > typec_unregister_port(typec->ports[i]->port); > } > } > > /* > - * Fake the alt mode structs until we actually start registering Type C port > - * and partner alt modes. > + * Register port alt modes with known values till we start retrieving > + * port capabilities from the EC. > */ > -static void cros_typec_register_port_altmodes(struct cros_typec_data *typec, > +static int cros_typec_register_port_altmodes(struct cros_typec_data *typec, > int port_num) > { > struct cros_typec_port *port = typec->ports[port_num]; > + struct typec_altmode_desc desc; > + struct typec_altmode *amode; > > /* All PD capable CrOS devices are assumed to support DP altmode. */ > - port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; > - port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; > + desc.svid = USB_TYPEC_DP_SID, > + desc.mode = USB_TYPEC_DP_MODE, > + desc.vdo = DP_PORT_VDO, > + amode = typec_port_register_altmode(port->port, &desc); > + if (IS_ERR(amode)) > + return PTR_ERR(amode); > + port->port_altmode[CROS_EC_ALTMODE_DP] = amode; > > /* > * Register TBT compatibility alt mode. The EC will not enter the mode > * if it doesn't support it, so it's safe to register it unconditionally > * here for now. > */ > - port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; > - port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; > + memset(&desc, 0, sizeof(desc)); > + desc.svid = USB_TYPEC_TBT_SID, > + desc.mode = TYPEC_ANY_MODE, > + amode = typec_port_register_altmode(port->port, &desc); > + if (IS_ERR(amode)) > + return PTR_ERR(amode); > + port->port_altmode[CROS_EC_ALTMODE_TBT] = amode; > > port->state.alt = NULL; > port->state.mode = TYPEC_STATE_USB; > port->state.data = NULL; > + > + return 0; > } > > static int cros_typec_init_ports(struct cros_typec_data *typec) > @@ -361,7 +386,11 @@ static int cros_typec_init_ports(struct cros_typec_data *typec) > dev_dbg(dev, "No switch control for port %d\n", > port_num); > > - cros_typec_register_port_altmodes(typec, port_num); > + ret = cros_typec_register_port_altmodes(typec, port_num); > + if (ret) { > + dev_err(dev, "Failed to register port altmodes\n"); > + goto unregister_ports; > + } > > cros_port->disc_data = devm_kzalloc(dev, EC_PROTO2_MAX_RESPONSE_SIZE, GFP_KERNEL); > if (!cros_port->disc_data) { > @@ -430,7 +459,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec, > data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE; > > if (!port->state.alt) { > - port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT]; > + port->state.alt = port->port_altmode[CROS_EC_ALTMODE_TBT]; > ret = cros_typec_usb_safe_state(port); > if (ret) > return ret; > @@ -472,7 +501,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, > /* Configuration VDO. */ > dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode); > if (!port->state.alt) { > - port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP]; > + port->state.alt = port->port_altmode[CROS_EC_ALTMODE_DP]; > ret = cros_typec_usb_safe_state(port); > if (ret) > return ret; > -- > 2.37.0.144.g8ac04bfd2-goog -- heikki ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array 2022-07-12 21:03 [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Prashant Malani 2022-07-12 21:03 ` [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes Prashant Malani @ 2022-07-18 8:37 ` Heikki Krogerus 2022-07-18 19:20 ` patchwork-bot+chrome-platform 2022-07-19 21:50 ` patchwork-bot+chrome-platform 3 siblings, 0 replies; 6+ messages in thread From: Heikki Krogerus @ 2022-07-18 8:37 UTC (permalink / raw) To: Prashant Malani; +Cc: linux-kernel, chrome-platform, bleung, Guenter Roeck On Tue, Jul 12, 2022 at 09:03:17PM +0000, Prashant Malani wrote: > Rename "p_altmode" to "port_altmode" which is a less ambiguous name for > the port_altmode struct array. > > Signed-off-by: Prashant Malani <pmalani@chromium.org> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> > --- > drivers/platform/chrome/cros_ec_typec.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) > > diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c > index d6088ba447af..b9848e80f372 100644 > --- a/drivers/platform/chrome/cros_ec_typec.c > +++ b/drivers/platform/chrome/cros_ec_typec.c > @@ -60,8 +60,7 @@ struct cros_typec_port { > uint8_t mux_flags; > uint8_t role; > > - /* Port alt modes. */ > - struct typec_altmode p_altmode[CROS_EC_ALTMODE_MAX]; > + struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX]; > > /* Flag indicating that PD partner discovery data parsing is completed. */ > bool sop_disc_done; > @@ -282,16 +281,16 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec, > struct cros_typec_port *port = typec->ports[port_num]; > > /* All PD capable CrOS devices are assumed to support DP altmode. */ > - port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; > - port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; > + port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; > + port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; > > /* > * Register TBT compatibility alt mode. The EC will not enter the mode > * if it doesn't support it, so it's safe to register it unconditionally > * here for now. > */ > - port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; > - port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; > + port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; > + port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; > > port->state.alt = NULL; > port->state.mode = TYPEC_STATE_USB; > @@ -431,7 +430,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec, > data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE; > > if (!port->state.alt) { > - port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT]; > + port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT]; > ret = cros_typec_usb_safe_state(port); > if (ret) > return ret; > @@ -473,7 +472,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, > /* Configuration VDO. */ > dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode); > if (!port->state.alt) { > - port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_DP]; > + port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP]; > ret = cros_typec_usb_safe_state(port); > if (ret) > return ret; > -- > 2.37.0.144.g8ac04bfd2-goog -- heikki ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array 2022-07-12 21:03 [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Prashant Malani 2022-07-12 21:03 ` [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes Prashant Malani 2022-07-18 8:37 ` [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Heikki Krogerus @ 2022-07-18 19:20 ` patchwork-bot+chrome-platform 2022-07-19 21:50 ` patchwork-bot+chrome-platform 3 siblings, 0 replies; 6+ messages in thread From: patchwork-bot+chrome-platform @ 2022-07-18 19:20 UTC (permalink / raw) To: Prashant Malani Cc: linux-kernel, chrome-platform, bleung, heikki.krogerus, groeck Hello: This series was applied to chrome-platform/linux.git (for-kernelci) by Prashant Malani <pmalani@chromium.org>: On Tue, 12 Jul 2022 21:03:17 +0000 you wrote: > Rename "p_altmode" to "port_altmode" which is a less ambiguous name for > the port_altmode struct array. > > Signed-off-by: Prashant Malani <pmalani@chromium.org> > --- > drivers/platform/chrome/cros_ec_typec.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) Here is the summary with links: - [1/2] platform/chrome: cros_ec_typec: Rename port altmode array https://git.kernel.org/chrome-platform/c/a47bc5a0c4c0 - [2/2] platform/chrome: cros_ec_typec: Register port altmodes https://git.kernel.org/chrome-platform/c/1ff5d97f070c You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array 2022-07-12 21:03 [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Prashant Malani ` (2 preceding siblings ...) 2022-07-18 19:20 ` patchwork-bot+chrome-platform @ 2022-07-19 21:50 ` patchwork-bot+chrome-platform 3 siblings, 0 replies; 6+ messages in thread From: patchwork-bot+chrome-platform @ 2022-07-19 21:50 UTC (permalink / raw) To: Prashant Malani Cc: linux-kernel, chrome-platform, bleung, heikki.krogerus, groeck Hello: This series was applied to chrome-platform/linux.git (for-next) by Prashant Malani <pmalani@chromium.org>: On Tue, 12 Jul 2022 21:03:17 +0000 you wrote: > Rename "p_altmode" to "port_altmode" which is a less ambiguous name for > the port_altmode struct array. > > Signed-off-by: Prashant Malani <pmalani@chromium.org> > --- > drivers/platform/chrome/cros_ec_typec.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) Here is the summary with links: - [1/2] platform/chrome: cros_ec_typec: Rename port altmode array https://git.kernel.org/chrome-platform/c/a47bc5a0c4c0 - [2/2] platform/chrome: cros_ec_typec: Register port altmodes https://git.kernel.org/chrome-platform/c/1ff5d97f070c You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-07-19 21:50 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-07-12 21:03 [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Prashant Malani 2022-07-12 21:03 ` [PATCH 2/2] platform/chrome: cros_ec_typec: Register port altmodes Prashant Malani 2022-07-18 8:38 ` Heikki Krogerus 2022-07-18 8:37 ` [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Heikki Krogerus 2022-07-18 19:20 ` patchwork-bot+chrome-platform 2022-07-19 21:50 ` patchwork-bot+chrome-platform
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