From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E30D7C433EF for ; Tue, 19 Jul 2022 19:11:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238930AbiGSTLz (ORCPT ); Tue, 19 Jul 2022 15:11:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235514AbiGSTLu (ORCPT ); Tue, 19 Jul 2022 15:11:50 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A67B9474E7 for ; Tue, 19 Jul 2022 12:11:49 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id x24-20020a17090ab01800b001f21556cf48so1083797pjq.4 for ; Tue, 19 Jul 2022 12:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=5euGlNmAtOuwJge1OAZFWWG5YnuElfsaMVS/8+pCung=; b=lYQH+CDAn8WlY9EcQ7lCQ2O1WMC+gU8t3Rx9MbHBA0vhwKJoliK4rvn1HphmSRntq4 Kg1d6NVzXVy58nXoP565l0UjAFOCEczZKjyLc6sSZnlWmWHs5hBUg18JWSanwXMYKXIG mt5mMAdmpMlVdS4ZqudxBwVFs9vW9mmvuNJglFRnNEnYGuHCBdwFHeK9q2oCcXG0OEXp PAf7c9M1SPksx49vKuh5Av3Y48SonMbZ5bljU4PXsLiAzr9vUEUsfPfzKGPCaB6E2Fyu nTUPeMmSNOUOTzc1uMTVKT1o7FgRnUE44iY9J2TpZuPEF+7qM6XI3PfO6jeMH3LIE6BT Tmng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=5euGlNmAtOuwJge1OAZFWWG5YnuElfsaMVS/8+pCung=; b=3qckysvoxhxUu7g8nzDVRLt83cUErcPnc6HkFO/jMpVyZjusDMIJbRi492cgeF5Jwv x2tV5Br+BgWSuuEsHl0QVOpVqkD1erbj/JMJWJNmB0IU5Hm20OoUm/Z3NRkjnQQT3W+0 vwNxC59hLGhcwxwNFCZBotsdMpFjdiAEzbvrR8znJ9wkFXhYbsAG7XYSooCgTmv1VgyF cnoNt/ECciHwSbTX/n0EqzOpf5HBvPyzmMdbAxZUadkezj8NmV6jrTX1oqguKmct9Ro0 +83XWEd3Z1MllHfWKsCM6qEjZlWsuNjsH6a/XcFQrb/cZPHmRH4FsHZxYFkDBDekImJ7 NqHA== X-Gm-Message-State: AJIora+mOtC5+w45eMNuniAjSaRf9nM67ZXBxRmGUUaSHhYSb9R48Sby i5cT3+JcNkx0xChI9ozFevSxaw== X-Google-Smtp-Source: AGRyM1ukVRoo46Z3XwAvvEFhfpu7v8Jc2npjQaPCc2VMImHDe3eUmh5Mh0gZd69IAhwax4PCXtNX1w== X-Received: by 2002:a17:90a:ce07:b0:1f0:d4b1:30a1 with SMTP id f7-20020a17090ace0700b001f0d4b130a1mr904119pju.165.1658257909015; Tue, 19 Jul 2022 12:11:49 -0700 (PDT) Received: from google.com (123.65.230.35.bc.googleusercontent.com. [35.230.65.123]) by smtp.gmail.com with ESMTPSA id u190-20020a6279c7000000b0052b433aa45asm9004344pfc.159.2022.07.19.12.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Jul 2022 12:11:48 -0700 (PDT) Date: Tue, 19 Jul 2022 19:11:44 +0000 From: Sean Christopherson To: Suravee Suthikulpanit Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, pbonzini@redhat.com, mlevitsk@redhat.com, jon.grimm@amd.com Subject: Re: [PATCH] KVM: SVM: Fix x2APIC MSRs interception Message-ID: References: <20220718083833.222117-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220718083833.222117-1-suravee.suthikulpanit@amd.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 18, 2022, Suravee Suthikulpanit wrote: > The index for svm_direct_access_msrs was incorrectly initialized with > the APIC MMIO register macros. Fix by introducing a macro for calculating > x2APIC MSRs. > > Fixes: 5c127c85472c ("KVM: SVM: Adding support for configuring x2APIC MSRs interception") > Cc: Maxim Levitsky > Signed-off-by: Suravee Suthikulpanit > --- > arch/x86/kvm/svm/svm.c | 52 ++++++++++++++++++++++-------------------- > 1 file changed, 27 insertions(+), 25 deletions(-) > > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index ba81a7e58f75..aef63aae922d 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -74,6 +74,8 @@ static uint64_t osvw_len = 4, osvw_status; > > static DEFINE_PER_CPU(u64, current_tsc_ratio); > > +#define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4)) Once this hits kvm/queue, I'll send a follow-up series to move X2APIC_MSR() to arch/x86/include/asm/apicdef.h. Non-KVM APIC support open code the calculation in multiple places, and both VMX and SVM now have their own definitions.