Re: Apple Thunderbolt Display chaining

[Mika Westerberg <mika.westerberg@linux.intel.com>]

Hi,

On Mon, Aug 08, 2022 at 07:55:14PM +0800, Brad Campbell wrote:
> 31:04.0 PCI bridge: Intel Corporation CV82524 Thunderbolt Controller [Light Ridge 4C 2010]

...

> 19:28:44 openat(AT_FDCWD, "/sys/bus/pci/devices/0000:31:04.0/config", O_RDONLY) = 3
> 19:28:44 pread64(3, "\206\200\23\25\7\0\20\0\0\0\4\6\20\0\1\0\0\0\0\0\0\0\0\000177\0\361\1\0\0\360\377\0\0\361\377\1\0\0\0\0\0\0\0\0\0\0\0\0\0\200\0\0\0\0\0\0\0\377\1\2\0", 64, 0) = 64
> 19:28:44 openat(AT_FDCWD, "/sys/bus/pci/devices/0000:31:04.0/vendor", O_RDONLY) = 4
> 19:28:44 read(4, "0x8086\n", 1024)      = 7

...

> 19:29:02 openat(AT_FDCWD, "/sys/bus/pci/devices/0000:31:04.0/config", O_RDONLY) = 3
> 19:29:02 pread64(3, "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377", 64, 0) = 64

It looks like the 31:04 PCIe downstream port and the device below are
not accessible anymore (we read 0xff from the config space if parse the
strace output correctly).

> 19:29:05 openat(AT_FDCWD, "/sys/bus/pci/devices/0000:33:03.0/config", O_RDONLY) = 3
> 19:29:05 pread64(3, "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377", 64, 0) = 64

Same here for the 33:03.

Now, this can happen if the Thunderbolt driver runtime suspends and
there is not device link in place from the TR tunneled PCIe downstream
ports towards the Thunderbolt controller. However, you have the
pcie_port_pm=off that should prevent it from happening (and the
Thunderbolt driver blocks runtime PM on TBT1 devices). Can you modify
drivers/pci/pci.c::pci_bridge_d3_possible() so that it looks like this

bool pci_bridge_d3_possible(struct pci_dev *bridge)
{
#if 0
	...
#else
	return false;
#endif
}

and try if that makes any difference? Probably no but worth a try
anyway.