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From: Ashok Raj <ashok.raj@intel.com>
To: Andrew Cooper <Andrew.Cooper3@citrix.com>
Cc: Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@alien8.de>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	Tony Luck <tony.luck@intel.com>,
	Dave Hansen <dave.hansen@intel.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	"luto@amacapital.net" <luto@amacapital.net>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Ashok Raj <ashok.raj@intel.com>
Subject: Re: [PATCH 5/5] x86/microcode: Handle NMI's during microcode update.
Date: Sun, 14 Aug 2022 14:41:18 +0000	[thread overview]
Message-ID: <YvkJjsdlDIcerqLg@araj-dh-work> (raw)
In-Reply-To: <328bf268-51b3-f9b2-1315-bac0e883d135@citrix.com>

Hi Andrew,

On Sun, Aug 14, 2022 at 11:58:17AM +0000, Andrew Cooper wrote:
> >> If I were implementing this, I would rendezvous via stop_machine as usual.  Then I would set a flag or install a handler indicating that we are doing a microcode update, send NMI-to-self, and rendezvous in the NMI handler and do the update.
> > Well, that is exactly what I did for the first attempt. The code looked so
> > beautiful in the eyes of the creator :-) but somehow I couldn't get it to
> > not lock up.
> 
> So the way we do this in Xen is to rendezvous in stop machine, then have
> only the siblings self-NMI.  The primary threads don't need to be in NMI
> context, because the WRMSR to trigger the update *is* atomic with NMIs.
> 
> However, you do need to make sure that the NMI wait loop knows not to
> wait for primary threads, otherwise you can deadlock when taking an NMI
> on a primary thread between setting up the NMI handler and actually
> issuing the update.
> 

I'm almost sure that was the deadlock I ran into. You are correct, the
primary thread doesn't need to be in NMI, since once the wrmsr starts,  it
can't be interrupted.

But the primary needs to wait until its own siblings have dropped into NMI.
Before proceeding to perform wrmsr.

in stop_machine() handler, primary thread waits for its thread siblings to
enter NMI and report itself. Siblings will simply self IPI and then proceed
to wait for exit_sync

then primary does the wrmsr flow
clears the wait_cpus mask so that secondary inside NMI hander can release
itself

resync at exit rendezvous.

I have this coded, will test and repost.

Cheers,
Ashok

      reply	other threads:[~2022-08-14 14:41 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-13 22:38 [PATCH 0/5] Adding more robustness to microcode loading Ashok Raj
2022-08-13 22:38 ` [PATCH 1/5] x86/microcode: Add missing documentation that late-load will taint kernel Ashok Raj
2022-08-15 19:40   ` [tip: x86/microcode] x86/microcode: Document the whole late loading problem tip-bot2 for Ashok Raj
2022-08-16  3:21     ` Ashok Raj
2022-08-16  7:40       ` Borislav Petkov
2022-08-16  6:51     ` Ingo Molnar
2022-08-16  7:46   ` tip-bot2 for Ashok Raj
2022-08-18 14:04   ` tip-bot2 for Ashok Raj
2022-08-13 22:38 ` [PATCH 2/5] x86/microcode/intel: Check against CPU signature before saving microcode Ashok Raj
2022-08-13 22:38 ` [PATCH 3/5] x86/microcode/intel: Allow a late-load only if a min rev is specified Ashok Raj
2022-08-15  7:43   ` Peter Zijlstra
2022-08-15 12:29     ` Ashok Raj
2022-08-15  7:46   ` Peter Zijlstra
2022-08-15 12:41     ` Ashok Raj
2022-08-15 13:04       ` Peter Zijlstra
2022-08-18 17:34     ` Dave Hansen
2022-08-13 22:38 ` [PATCH 4/5] x86/microcode: Avoid any chance of MCE's during microcode update Ashok Raj
2022-08-13 22:38 ` [PATCH 5/5] x86/microcode: Handle NMI's " Ashok Raj
2022-08-14  0:13   ` Andy Lutomirski
2022-08-14  1:19     ` Andy Lutomirski
2022-08-14  3:05       ` Ashok Raj
2022-08-14  2:54     ` Ashok Raj
2022-08-14 11:58       ` Andrew Cooper
2022-08-14 14:41         ` Ashok Raj [this message]

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