Re: [tip: x86/microcode] x86/microcode: Document the whole late loading problem

[Ashok Raj <ashok.raj@intel.com>]

Hi Boris,

Seems like there is an extraneous 'e' at the start of a line. Think this
existed in my patch patch, I noticed internally due to the 0day report that
a newline was missing.


On Mon, Aug 15, 2022 at 07:40:05PM -0000, tip-bot2 for Ashok Raj wrote:
[snip]
> diff --git a/Documentation/admin-guide/tainted-kernels.rst b/Documentation/admin-guide/tainted-kernels.rst
> index 7d80e8c..e59a710 100644
> --- a/Documentation/admin-guide/tainted-kernels.rst
> +++ b/Documentation/admin-guide/tainted-kernels.rst
> @@ -134,7 +134,13 @@ More detailed explanation for tainting
>         scsi/snic on something else than x86_64, scsi/ips on non
>         x86/x86_64/itanium, have broken firmware settings for the
>         irqchip/irq-gic on arm64 ...).
> -
> +     - x86/x86_64: Microcode late loading is dangerous and will result in
> +       tainting the kernel. It requires that all CPUs rendezvous to make sure
> +       the update happens when the system is as quiescent as possible. However,
> +       a higher priority MCE/SMI/NMI can move control flow away from that
> +       rendezvous and interrupt the update, which can be detrimental to the
> +       machine.
> +e

^^^^^^