From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8590ECAAD5 for ; Mon, 12 Sep 2022 13:05:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229851AbiILNF4 (ORCPT ); Mon, 12 Sep 2022 09:05:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229646AbiILNFy (ORCPT ); Mon, 12 Sep 2022 09:05:54 -0400 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [IPv6:2001:4d48:ad52:32c8:5054:ff:fe00:142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2063125C4B for ; Mon, 12 Sep 2022 06:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Sender:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=R64HR0KrGmiwNZpIuE4KD+OwisrLI4ElftJ4XXe8mos=; b=hY9ofewwhZNIIYsV4huXDbLJZv e927eTa0EDN9+LxuNoEhkq98XSC7Kyjcr0W7H1frx9G2Of+0igm2sZPoWjyNVzcUAK/GHdMzaAiwV /YN9icfPuisPpwR7y7/ASk+ToQ/Ej0nJ9KG7sMP7JU3d2st+lw15GwA2bA00GdxaR1kZPTdWRXH6l r8/p3N6LTgxgZtD6JQBQ03LUxISLH1fYhmhZI/9Irmi3WvajeMoNVPb4Te/ELIdPMOH19CsrGuN7L d5c4YYk4MbYV0sIQR2qFACSu1ImXFula+cA6qgXddAyvZ/jyHB0jtwgrycSjGz23u3V8BjB94zLbB +Ow9/7+A==; Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:34262) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oXj8B-0001hu-WE; Mon, 12 Sep 2022 14:05:44 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1oXj8A-00087m-0O; Mon, 12 Sep 2022 14:05:42 +0100 Date: Mon, 12 Sep 2022 14:05:41 +0100 From: "Russell King (Oracle)" To: Catalin Marinas Cc: George Pee , Robin Murphy , "Kirill A. Shutemov" , Austin Kim , Ard Biesheuvel , Mike Rapoport , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] Report support for optional ARMv8.2 half-precision floating point extension Message-ID: References: <20220901141307.2361752-1-georgepee@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: Russell King (Oracle) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 09, 2022 at 04:05:53PM +0100, Catalin Marinas wrote: > On Fri, Sep 09, 2022 at 09:57:39AM -0500, George Pee wrote: > > The details are here. I originally thought it was a compiler bug > > because it first showed up after a toolchain update. > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106763 > > > > Since FP16 is an optional extension, wouldn't it be beneficial to a > > user who compiled some userspace float16 code using gcc > > -mcpu=cortex-a55 which ran on a cortex-a55 with FP16 extensions but > > SIGILL'd on a cortex-a55 w/o FP16? > > (please don't top-post) > > My point is that if the kernel doesn't have full support for FP16, it > shouldn't advertise it to user even if the hardware supports it. If you > fix the kernel to properly handle FP16 on supporting hardware, then the > HWCAP part is fine by me. Presumably, the only CPUs that are going to support FP16 will have non-trapping floating point, so the support code shouldn't be entered at any time to emulate a half-precision instruction, but only to handle the lazy restore of the thread's floating point registers? -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!