Re: [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs

[Robert Richter <rrichter@amd.com>]

On 31.08.22 13:16:34, Jonathan Cameron wrote:
> On Wed, 31 Aug 2022 10:16:02 +0200
> Robert Richter <rrichter@amd.com> wrote:

> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> > index 88bbd2bb61fc..56b2d222afcc 100644
> > --- a/drivers/cxl/acpi.c
> > +++ b/drivers/cxl/acpi.c
> > @@ -471,13 +471,52 @@ static int cxl_setup_component_reg(struct device *parent,
> >  	return 0;
> >  }
> >  
> > +static int cxl_enumerate_rch_ports(struct device *root_dev,
> > +				   struct cxl_port *cxl_root,
> > +				   struct pci_host_bridge *host,
> > +				   resource_size_t component_reg_phys,
> > +				   int port_id)
> > +{
> > +	struct cxl_dport *dport;
> > +	struct cxl_port *port;
> > +	struct pci_dev *pdev;
> > +
> > +	dport = devm_cxl_add_dport(cxl_root, &host->dev, port_id,
> > +				   component_reg_phys);
> > +	if (IS_ERR(dport))
> > +		return PTR_ERR(dport);
> > +
> > +	port = devm_cxl_add_port(root_dev, &host->dev,
> > +				 component_reg_phys, dport);
> > +	if (IS_ERR(port))
> > +		return PTR_ERR(port);
> > +
> > +	pdev = pci_get_slot(host->bus, PCI_DEVFN(0, 0));
> > +	if (!pdev)
> > +		return -ENXIO;
> > +
> > +	/* Note: The endpoint provides the component reg base. */
> 
> I'm not sure what this comment means.  Which component reg base?

There is no component_reg_phys provided here, so the addr is
CXL_RESOURCE_NONE.

Will improve the comment.

> 
> > +	dport = devm_cxl_add_dport(port, &pdev->dev, 0,
> > +				   CXL_RESOURCE_NONE);
> 
> Trivial: No need to wrap the above.

Right.

Thanks,

-Robert