From: Johan Hovold <johan@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: andersson@kernel.org, kishon@ti.com,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
Date: Tue, 20 Sep 2022 11:29:01 +0200 [thread overview]
Message-ID: <YymH3XCz2r/pj0xY@hovoldconsulting.com> (raw)
In-Reply-To: <YylhpBtz8d2dqJhv@matsya>
On Tue, Sep 20, 2022 at 12:15:56PM +0530, Vinod Koul wrote:
> On 10-09-22, 12:08, Manivannan Sadhasivam wrote:
> > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> > and QPHY_V5_PCS_EQ_CONFIG3.
> >
> > This causes high latency when ASPM is enabled, so fix it!
> >
> > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > index 61a44519f969..cca6455ec98c 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > @@ -11,7 +11,7 @@
> > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
Why are you removing these defines? (They are correct for sc8280xp.)
> > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
>
> This conflicts with c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
>
> where QPHY_V5_PCS_EQ_CONFIG5 was added as 0x1e0
>
> Do we have a different v5 for SM8450 and SC8280XP?
I can confirm that the PCS_EQ_CONFIG defines added for sc8280xp matches
the vendor's headers for both the combo and USB PHYs.
Johan
next prev parent reply other threads:[~2022-09-20 9:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-10 6:38 [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Manivannan Sadhasivam
2022-09-20 6:45 ` Vinod Koul
2022-09-20 9:29 ` Johan Hovold [this message]
2022-09-21 13:06 ` Dmitry Baryshkov
2022-10-26 14:31 ` Manivannan Sadhasivam
2022-10-26 16:45 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YymH3XCz2r/pj0xY@hovoldconsulting.com \
--to=johan@kernel.org \
--cc=andersson@kernel.org \
--cc=kishon@ti.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox