[RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization

[RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization

[Sarath Babu Naidu Gaddam]

Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is
to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.

This patchset does feature addition and optimization to support axidma
integration with axiethernet network driver. Once axidma version is
accepted mcdma specific changes will be added in followup version.

Changes for V2:
- Use metadata API[1] for passing metadata from dma to netdev client.
- Read irq-delay from DT.
- Remove desc_callback_valid check.
- Addressed RFC v1 comments[2].
- Minor code refactoring.

Changes for V3:
- Add device_config support for passing any dma client data.
- Address RFC v2 comments.
    - remove hardcoding for axidma_tx_segment.
    - Below review comment is in pipeline. We are facing a race issue when
      addressing it. we will fix it in the next version.
      "chan->idle = true; in xilinx_dma_irq_handler() needs to be gated on
       the active_list being empty".

Comments, suggestions are very welcome

Radhey Shyam Pandey (7):
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
    property
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
  dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
  dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
  dmaengine: xilinx_dma: Freeup active list based on descriptor
    completion bit
  dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
    usecase
  dmaengine: xilinx_dma: Program interrupt delay timeout

Sarath Babu Naidu Gaddam (1):
  dmaengine: xilinx_dma: Add device_config support

 .../bindings/dma/xilinx/xilinx_dma.txt        |   4 +
 drivers/dma/xilinx/xilinx_dma.c               | 107 ++++++++++++++++--
 include/linux/dma/xilinx_dma.h                |  16 +++
 3 files changed, 115 insertions(+), 12 deletions(-)

-- 
2.25.1

[RFC V3 PATCH 1/8] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Add an optional DMA property 'xlnx,axistream-connected'. This can be
specified to indicate that DMA is connected to a streaming IP in the
hardware design and dma driver needs to do some additional handling
i.e pass metadata and perform streaming IP specific configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3:
- Add Rob acked-by.

Changes in V2:
- Rename xlnx,axieth-connected to xlnx,axistream-connected to
  make it generic.
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index d1700a5c36bf..18445aa092ab 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,6 +49,8 @@ Optional properties for AXI DMA and MCDMA:
 	register as configured in h/w. Takes values {8...26}. If the property
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
+
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1

[RFC V3 PATCH 2/8] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
timeout value and causes the DMA engine to generate an interrupt after the
delay time period has expired. Timer begins counting at the end of a packet
and resets with receipt of a new packet or a timeout event occurs.

This property is useful when AXI DMA is connected to the streaming IP i.e
axiethernet where inter packet latency is critical while still taking the
benefit of interrupt coalescing.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3:
- Add rob acked-by.

Changes in V2:
- New patch. Introduce xlnx,irq-delay property for low latency usecases.
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index 18445aa092ab..9793523633a4 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -50,7 +50,9 @@ Optional properties for AXI DMA and MCDMA:
 	is missing or invalid then the default value 23 is used. This is the
 	maximum value that is supported by all IP versions.
 - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
-
+- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
+	0-255. Setting this value to zero disables the delay timer interrupt.
+	1 timeout interval = 125 * clock period of SG clock.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
 	It takes following values:
-- 
2.25.1

[RFC V3 PATCH 3/8] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Read DT property to check if AXI DMA is connected to streaming IP
i.e axiethernet. If connected pass AXI4-Stream control words to
dma client using metadata_ops dmaengine API.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3:
- None.

Changes in V2:
- Use descriptor metadata API to pass control words to dma client.
- Rephrased commit description to be inline with implementation.
---
 drivers/dma/xilinx/xilinx_dma.c | 37 +++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 6276934d4d2b..12b1281b19bf 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -493,6 +493,7 @@ struct xilinx_dma_config {
  * @s2mm_chan_id: DMA s2mm channel identifier
  * @mm2s_chan_id: DMA mm2s channel identifier
  * @max_buffer_len: Max buffer length
+ * @has_axistream_connected: AXI DMA connected to AXI Stream IP
  */
 struct xilinx_dma_device {
 	void __iomem *regs;
@@ -511,6 +512,7 @@ struct xilinx_dma_device {
 	u32 s2mm_chan_id;
 	u32 mm2s_chan_id;
 	u32 max_buffer_len;
+	bool has_axistream_connected;
 };
 
 /* Macros */
@@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
 	}
 }
 
+/**
+ * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length
+ * @tx: async transaction descriptor
+ * @payload_len: metadata payload length
+ * @max_len: metadata max length
+ * Return: The app field pointer.
+ */
+static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
+					 size_t *payload_len, size_t *max_len)
+{
+	struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
+	struct xilinx_axidma_tx_segment *seg;
+
+	*max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
+	seg = list_first_entry(&desc->segments,
+			       struct xilinx_axidma_tx_segment, node);
+	return seg->hw.app;
+}
+
+static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
+	.get_ptr = xilinx_dma_get_metadata_ptr,
+};
+
 /* -----------------------------------------------------------------------------
  * Descriptors and segments alloc and free
  */
@@ -2326,6 +2351,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
 		segment->hw.control |= XILINX_DMA_BD_EOP;
 	}
 
+	if (chan->xdev->has_axistream_connected)
+		desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
+
 	return &desc->async_tx;
 
 error:
@@ -3064,6 +3092,11 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+		xdev->has_axistream_connected =
+			of_property_read_bool(node, "xlnx,axistream-connected");
+	}
+
 	if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
 		err = of_property_read_u32(node, "xlnx,num-fstores",
 					   &num_frames);
@@ -3089,6 +3122,10 @@ static int xilinx_dma_probe(struct platform_device *pdev)
 	else
 		xdev->ext_addr = false;
 
+	/* Set metadata mode */
+	if (xdev->has_axistream_connected)
+		xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE;
+
 	/* Set the dma mask bits */
 	dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
 
-- 
2.25.1

[RFC V3 PATCH 4/8] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Increase AXI DMA transaction segments count to ensure that even in
high load we always get a free segment in prepare descriptor for a
DMA_SLAVE transaction.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3 and V2:
- None
---
 drivers/dma/xilinx/xilinx_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 12b1281b19bf..8c6065cbda79 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -178,7 +178,7 @@
 #define XILINX_DMA_BD_SOP		BIT(27)
 #define XILINX_DMA_BD_EOP		BIT(26)
 #define XILINX_DMA_COALESCE_MAX		255
-#define XILINX_DMA_NUM_DESCS		255
+#define XILINX_DMA_NUM_DESCS		512
 #define XILINX_DMA_NUM_APP_WORDS	5
 
 /* AXI CDMA Specific Registers/Offsets */
-- 
2.25.1

[RFC V3 PATCH 5/8] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

AXIDMA IP in SG mode sets completion bit to 1 when the transfer is
completed. Read this bit to move descriptor from active list to the
done list. This feature is needed when interrupt delay timeout and
IRQThreshold is enabled i.e Dly_IrqEn is triggered w/o completing
interrupt threshold.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3:
- Addressed RFC V2 review comment in xilinx_dma_complete_descriptor.
  "remove hardcoding for axidma_tx_segment".

- Below review comment is in pipeline. We are facing a race issue when
  addressing it. we will fix it in the next version.
  "chan->idle = true; in xilinx_dma_irq_handler() needs to be gated on
   the active_list being empty".

Changes in V2:
- Check BD completion bit only for SG mode.
- Modify the logic to have early return path.
---
 drivers/dma/xilinx/xilinx_dma.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 8c6065cbda79..1488cc6a299a 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -177,6 +177,7 @@
 #define XILINX_DMA_CR_COALESCE_SHIFT	16
 #define XILINX_DMA_BD_SOP		BIT(27)
 #define XILINX_DMA_BD_EOP		BIT(26)
+#define XILINX_DMA_BD_COMP_MASK		BIT(31)
 #define XILINX_DMA_COALESCE_MAX		255
 #define XILINX_DMA_NUM_DESCS		512
 #define XILINX_DMA_NUM_APP_WORDS	5
@@ -1706,6 +1707,14 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
 		return;
 
 	list_for_each_entry_safe(desc, next, &chan->active_list, node) {
+		if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+			struct xilinx_axidma_tx_segment *seg;
+
+			seg = list_last_entry(&desc->segments,
+					      struct xilinx_axidma_tx_segment, node);
+			if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
+				break;
+		}
 		if (chan->has_sg && chan->xdev->dma_config->dmatype !=
 		    XDMA_TYPE_VDMA)
 			desc->residue = xilinx_dma_get_residue(chan, desc);
-- 
2.25.1

[RFC V3 PATCH 6/8] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Schedule tasklet with high priority to ensure that callback processing
is prioritized. It improves throughput for netdev dma clients.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V2 and V3:
- None
---
 drivers/dma/xilinx/xilinx_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 1488cc6a299a..8126a56980f2 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1848,7 +1848,7 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
 		spin_unlock(&chan->lock);
 	}
 
-	tasklet_schedule(&chan->tasklet);
+	tasklet_hi_schedule(&chan->tasklet);
 	return IRQ_HANDLED;
 }
 
-- 
2.25.1

[RFC V3 PATCH 7/8] dmaengine: xilinx_dma: Program interrupt delay timeout

[Sarath Babu Naidu Gaddam]

From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured. It also remove the placeholder
for delay interrupt and merge it with frame completion interrupt.
Since by default interrupt delay timeout is disabled this feature
addition has no functional impact on VDMA and CDMA IP's.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
Changes in V3:
- None.

Changes in V2:
- Read irq delay timeout value from DT.
- Merge interrupt processing for frame done and delay interrupt.
---
 drivers/dma/xilinx/xilinx_dma.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 8126a56980f2..bd8f09837141 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -173,8 +173,10 @@
 #define XILINX_DMA_MAX_TRANS_LEN_MAX	23
 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX	26
 #define XILINX_DMA_CR_COALESCE_MAX	GENMASK(23, 16)
+#define XILINX_DMA_CR_DELAY_MAX		GENMASK(31, 24)
 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK	BIT(4)
 #define XILINX_DMA_CR_COALESCE_SHIFT	16
+#define XILINX_DMA_CR_DELAY_SHIFT	24
 #define XILINX_DMA_BD_SOP		BIT(27)
 #define XILINX_DMA_BD_EOP		BIT(26)
 #define XILINX_DMA_BD_COMP_MASK		BIT(31)
@@ -411,6 +413,7 @@ struct xilinx_dma_tx_descriptor {
  * @stop_transfer: Differentiate b/w DMA IP's quiesce
  * @tdest: TDEST value for mcdma
  * @has_vflip: S2MM vertical flip
+ * @irq_delay: Interrupt delay timeout
  */
 struct xilinx_dma_chan {
 	struct xilinx_dma_device *xdev;
@@ -449,6 +452,7 @@ struct xilinx_dma_chan {
 	int (*stop_transfer)(struct xilinx_dma_chan *chan);
 	u16 tdest;
 	bool has_vflip;
+	u8 irq_delay;
 };
 
 /**
@@ -1561,6 +1565,9 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 	if (chan->has_sg)
 		xilinx_write(chan, XILINX_DMA_REG_CURDESC,
 			     head_desc->async_tx.phys);
+	reg  &= ~XILINX_DMA_CR_DELAY_MAX;
+	reg  |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT;
+	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
 
 	xilinx_dma_start(chan);
 
@@ -1896,15 +1903,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
 		}
 	}
 
-	if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
-		/*
-		 * Device takes too long to do the transfer when user requires
-		 * responsiveness.
-		 */
-		dev_dbg(chan->dev, "Inter-packet latency too long\n");
-	}
-
-	if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
+	if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ |
+		      XILINX_DMA_DMASR_DLY_CNT_IRQ)) {
 		spin_lock(&chan->lock);
 		xilinx_dma_complete_descriptor(chan);
 		chan->idle = true;
@@ -2831,6 +2831,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
 	/* Retrieve the channel properties from the device tree */
 	has_dre = of_property_read_bool(node, "xlnx,include-dre");
 
+	of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay);
+
 	chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode");
 
 	err = of_property_read_u32(node, "xlnx,datawidth", &value);
-- 
2.25.1

[RFC V3 PATCH 8/8] dmaengine: xilinx_dma: Add device_config support

[Sarath Babu Naidu Gaddam]

DMA clients (ethernet driver) can use this interface to pass get/set
coalesce information.

Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
---
At present device_config support to program coalesce is only for AXIDMA
and once the RFC is accepted it will extended to other IP variants.

Changes in V3:
- New patch.
---
 drivers/dma/xilinx/xilinx_dma.c | 37 ++++++++++++++++++++++++++++++++-
 include/linux/dma/xilinx_dma.h  | 16 ++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index bd8f09837141..0a994c5f3ae0 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -414,6 +414,7 @@ struct xilinx_dma_tx_descriptor {
  * @tdest: TDEST value for mcdma
  * @has_vflip: S2MM vertical flip
  * @irq_delay: Interrupt delay timeout
+ * @has_static_coalesce: Used to check static/dynamic coalesce selection
  */
 struct xilinx_dma_chan {
 	struct xilinx_dma_device *xdev;
@@ -453,6 +454,7 @@ struct xilinx_dma_chan {
 	u16 tdest;
 	bool has_vflip;
 	u8 irq_delay;
+	u8 has_static_coalesce;
 };
 
 /**
@@ -1555,7 +1557,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
 
 	reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
 
-	if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
+	if (!(chan->has_static_coalesce) && chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) {
 		reg &= ~XILINX_DMA_CR_COALESCE_MAX;
 		reg |= chan->desc_pendingcount <<
 				  XILINX_DMA_CR_COALESCE_SHIFT;
@@ -1696,6 +1698,39 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan)
 static int xilinx_dma_device_config(struct dma_chan *dchan,
 				    struct dma_slave_config *config)
 {
+	struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
+	u32 regval;
+
+	if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+		struct xilinx_peri_config *pconfig = config->peripheral_config;
+
+		if (!pconfig || config->peripheral_size != sizeof(*pconfig))
+			return -EINVAL;
+
+		switch (pconfig->cmd) {
+		case XILINX_DMA_GET_COALESCE:
+			regval = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
+			regval &= XILINX_DMA_CR_COALESCE_MAX;
+			*((int *)pconfig->data) = regval >> XILINX_DMA_CR_COALESCE_SHIFT;
+
+			break;
+		case XILINX_DMA_SET_COALESCE:
+			if ((*(int *)pconfig->data) <= XILINX_DMA_COALESCE_MAX) {
+				regval = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
+				regval &= ~XILINX_DMA_CR_COALESCE_MAX;
+				regval |= ((*(int *)pconfig->data) <<
+						 XILINX_DMA_CR_COALESCE_SHIFT);
+
+				dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, regval);
+				chan->has_static_coalesce = 1;
+			}
+
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
 	return 0;
 }
 
diff --git a/include/linux/dma/xilinx_dma.h b/include/linux/dma/xilinx_dma.h
index 0dde1a46ab75..ce0267baf5eb 100644
--- a/include/linux/dma/xilinx_dma.h
+++ b/include/linux/dma/xilinx_dma.h
@@ -41,5 +41,21 @@ struct xilinx_vdma_config {
 
 int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
 					struct xilinx_vdma_config *cfg);
+/**
+ * struct xilinx_peri_config -Configuration structure for user
+ * configurable commands and associated data.
+ *cmd:          cmd for passing any slave info. Example: ethtool get/set coalesce
+ *data:         data for cmd argument
+ */
+struct xilinx_peri_config {
+	int cmd;
+	void *data;
+};
+
+/**
+ * XILINX_DMA_GET/SET COALSCE -setting IP coalesce parameters
+ */
+#define XILINX_DMA_GET_COALESCE            1
+#define XILINX_DMA_SET_COALESCE            2
 
 #endif
-- 
2.25.1

Re: [RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization

[Vinod Koul]

On 20-09-22, 11:21, Sarath Babu Naidu Gaddam wrote:
> Some background about the patch series: Xilinx Axi Ethernet device driver
> (xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is
> to refactor axiethernet driver and use existing AXI DMA driver using
> DMAEngine API.
> 
> This patchset does feature addition and optimization to support axidma
> integration with axiethernet network driver. Once axidma version is
> accepted mcdma specific changes will be added in followup version.

why is this tagged RFC? Is it not ready for merge?

> 
> Changes for V2:
> - Use metadata API[1] for passing metadata from dma to netdev client.
> - Read irq-delay from DT.
> - Remove desc_callback_valid check.
> - Addressed RFC v1 comments[2].
> - Minor code refactoring.
> 
> Changes for V3:
> - Add device_config support for passing any dma client data.
> - Address RFC v2 comments.
>     - remove hardcoding for axidma_tx_segment.
>     - Below review comment is in pipeline. We are facing a race issue when
>       addressing it. we will fix it in the next version.
>       "chan->idle = true; in xilinx_dma_irq_handler() needs to be gated on
>        the active_list being empty".
> 
> Comments, suggestions are very welcome
> 
> Radhey Shyam Pandey (7):
>   dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
>     property
>   dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
>   dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
>   dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
>   dmaengine: xilinx_dma: Freeup active list based on descriptor
>     completion bit
>   dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
>     usecase
>   dmaengine: xilinx_dma: Program interrupt delay timeout
> 
> Sarath Babu Naidu Gaddam (1):
>   dmaengine: xilinx_dma: Add device_config support
> 
>  .../bindings/dma/xilinx/xilinx_dma.txt        |   4 +
>  drivers/dma/xilinx/xilinx_dma.c               | 107 ++++++++++++++++--
>  include/linux/dma/xilinx_dma.h                |  16 +++
>  3 files changed, 115 insertions(+), 12 deletions(-)
> 
> -- 
> 2.25.1

-- 
~Vinod

RE: [RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization

[Pandey, Radhey Shyam]

> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: Tuesday, September 20, 2022 4:57 PM
> To: Gaddam, Sarath Babu Naidu <sarath.babu.naidu.gaddam@amd.com>
> Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> lars@metafoo.de; adrianml@alumnos.upm.es; dmaengine@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>; Pandey,
> Radhey Shyam <radhey.shyam.pandey@amd.com>; Sarangi, Anirudha
> <anirudha.sarangi@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>; git@xilinx.com; git (AMD-Xilinx)
> <git@amd.com>
> Subject: Re: [RFC V3 PATCH 0/8] Xilinx DMA enhancements and optimization
> 
> On 20-09-22, 11:21, Sarath Babu Naidu Gaddam wrote:
> > Some background about the patch series: Xilinx Axi Ethernet device
> > driver
> > (xilinx_axienet_main.c) currently has axi-dma code inside it. The goal
> > is to refactor axiethernet driver and use existing AXI DMA driver
> > using DMAEngine API.
> >
> > This patchset does feature addition and optimization to support axidma
> > integration with axiethernet network driver. Once axidma version is
> > accepted mcdma specific changes will be added in followup version.
> 
> why is this tagged RFC? Is it not ready for merge?

To recap - In v3, the new addition is "[PATCH 8/8] dmaengine: 
xilinx_dma: Add device_config support" along with addressing 
RFC v2 comment. 

8/8 is initial proposal on how to implement coalesce feature in
dmaengine driver to support ethernet usecases. Thought was
that it's better to have this idea reviewed as RFC before 
extending the logic for other IP variants and spin sanity test
all usecases. 

Fallback option is to split this series and send patches which are
already reviewed in RFC v2 as PATCH and only 8/8 (which need 
more discussion/framework extension) as RFC?
Let me know your thoughts. 

Thanks,
Radhey
> 
> >
> > Changes for V2:
> > - Use metadata API[1] for passing metadata from dma to netdev client.
> > - Read irq-delay from DT.
> > - Remove desc_callback_valid check.
> > - Addressed RFC v1 comments[2].
> > - Minor code refactoring.
> >
> > Changes for V3:
> > - Add device_config support for passing any dma client data.
> > - Address RFC v2 comments.
> >     - remove hardcoding for axidma_tx_segment.
> >     - Below review comment is in pipeline. We are facing a race issue when
> >       addressing it. we will fix it in the next version.
> >       "chan->idle = true; in xilinx_dma_irq_handler() needs to be gated on
> >        the active_list being empty".
> >
> > Comments, suggestions are very welcome
> >
> > Radhey Shyam Pandey (7):
> >   dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
> >     property
> >   dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
> >   dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
> >   dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
> >   dmaengine: xilinx_dma: Freeup active list based on descriptor
> >     completion bit
> >   dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
> >     usecase
> >   dmaengine: xilinx_dma: Program interrupt delay timeout
> >
> > Sarath Babu Naidu Gaddam (1):
> >   dmaengine: xilinx_dma: Add device_config support
> >
> >  .../bindings/dma/xilinx/xilinx_dma.txt        |   4 +
> >  drivers/dma/xilinx/xilinx_dma.c               | 107 ++++++++++++++++--
> >  include/linux/dma/xilinx_dma.h                |  16 +++
> >  3 files changed, 115 insertions(+), 12 deletions(-)
> >
> > --
> > 2.25.1
> 
> --
> ~Vinod