[PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings

Hal Feng
2022-09-30T05:57:00Z

From: Emil Renner Berthing <kernel@esmil.dk>

Add bindings for the always-on clock generator on the JH7110
RISC-V SoC by StarFive Technology Ltd.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
.../clock/starfive,jh7110-clkgen-aon.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
new file mode 100644
index 000000000000..029ff57b9e3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-aon.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+ - Xingyu Wu <xingyu.wu@linux.starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-clkgen-aon
+
+ clocks:
+ items:
+ - description: Main Oscillator
+ - description: RTC clock
+ - description: RMII reference clock
+ - description: RGMII RX clock
+ - description: STG AXI/AHB clock
+ - description: APB Bus clock
+
+ clock-names:
+ items:
+ - const: osc
+ - const: clk_rtc
+ - const: gmac0_rmii_refin
+ - const: gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus_func
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive-jh7110-aon.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7110-sys.h>
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ clocks = <&osc>, <&clk_rtc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS_FUNC>;
+ clock-names = "osc", "clk_rtc",
+ "gmac0_rmii_refin", "gmac0_rgmii_rxin",
+ "stg_axiahb", "apb_bus_func";
+ #clock-cells = <1>;
+ };
--
2.17.1