From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Jacopo Mondi" <jacopo@jmondi.org>,
"Niklas Söderlund" <niklas.soderlund@ragnatech.se>,
"Sakari Ailus" <sakari.ailus@linux.intel.com>,
"Hans Verkuil" <hverkuil-cisco@xs4all.nl>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
"Biju Das" <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 2/4] media: dt-bindings: Document Renesas RZ/G2L CRU block
Date: Sat, 1 Oct 2022 00:05:25 +0300 [thread overview]
Message-ID: <YzdaFRA0L+qKbfMx@pendragon.ideasonboard.com> (raw)
In-Reply-To: <CA+V-a8vaHPbXQWyMeVWsFaf3mUSAECcJiiww5xmhC99+zm3SuQ@mail.gmail.com>
Hi Prabhakar,
On Fri, Sep 30, 2022 at 11:49:22AM +0100, Lad, Prabhakar wrote:
> On Thu, Sep 22, 2022 at 2:46 PM Laurent Pinchart wrote:
> > On Wed, Sep 21, 2022 at 08:58:26PM +0200, Krzysztof Kozlowski wrote:
> > > On 21/09/2022 19:29, Laurent Pinchart wrote:
> > > >>>>> + clock-names:
> > > >>>>> + items:
> > > >>>>> + - const: vclk
> > > >>>>> + - const: pclk
> > > >>>>> + - const: aclk
> > > >>>>
> > > >>>> Drop the "clk" suffixes. Remaining names could be made a bit more readable.
> > > >>>
> > > >>> These names come from the documentation, isn't it better to match the
> > > >>> datasheet ?
> > > >>
> > > >> If datasheet calls it "vclk_really_clk_it_is_clk_clk", it's not the
> > > >> reason to use it. :)
> > > >>
> > > >> The "clk" is redundant even if the hardware engineer thought different.
> > > >>
> > > >> The same for IRQs ("tx" not "txirq"), for dmas ("tx" not "txdma").
> > > >
> > > > I'd argue that naming clocks "v", "p" and "a" would be less readable and
> > > > more confusing. Is this a new rule ?
> > >
> > > Not really, but also it's only a style issue.
> > >
> > > Indeed "v" and "p" are not much better... but still "vclk" does not
> > > bring any additional information over "v". It's redundant.
> > >
> > > You can also drop entire entry - unless it helps in particular
> > > implementation.
> >
> > There are multiple clocks, so I think names are better than indices. If
> > you really insist we could name them "v", "p" and "a", but I think the
> > clk suffix here improves readability. If those clocks were named
> > "videoclk", "pixelclk" and "axiclk" I'd be fine dropping the suffix, but
> > that's not the case here.
>
> I have got the below details from the HW team:
>
> CRU_SYSCLK -> System clock for CSI-2 DPHY
> CRU_VCLK -> video clock
> CRU_PCLK -> APB clock
> CRU_ACLK -> AXI clock
>
> So I'll rename the clocks to below respectively:
>
> + clock-names:
> + items:
> + - const: system
> + - const: video
> + - const: apb
> + - const: axi
>
> Does the above sound good?
That's great, thank you !
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2022-09-30 21:05 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 23:04 [PATCH v2 0/4] Add driver for CSI2 and CRU modules found on Renesas RZ/G2L SoC Lad Prabhakar
2022-09-05 23:04 ` [PATCH v2 1/4] media: dt-bindings: Document Renesas RZ/G2L CSI-2 block Lad Prabhakar
2022-09-08 11:38 ` Krzysztof Kozlowski
2022-09-08 11:39 ` Krzysztof Kozlowski
2022-09-21 12:31 ` Lad, Prabhakar
2022-09-21 15:49 ` Krzysztof Kozlowski
2022-09-05 23:04 ` [PATCH v2 2/4] media: dt-bindings: Document Renesas RZ/G2L CRU block Lad Prabhakar
2022-09-08 11:40 ` Krzysztof Kozlowski
2022-09-21 12:43 ` Laurent Pinchart
2022-09-21 15:51 ` Krzysztof Kozlowski
2022-09-21 17:29 ` Laurent Pinchart
2022-09-21 18:58 ` Krzysztof Kozlowski
2022-09-22 13:46 ` Laurent Pinchart
2022-09-30 10:49 ` Lad, Prabhakar
2022-09-30 12:07 ` Krzysztof Kozlowski
2022-09-30 21:05 ` Laurent Pinchart [this message]
2022-09-05 23:04 ` [PATCH v2 3/4] media: platform: Add Renesas RZ/G2L MIPI CSI-2 receiver driver Lad Prabhakar
2022-09-21 16:12 ` Laurent Pinchart
2022-09-22 12:08 ` Lad, Prabhakar
2022-09-22 12:34 ` Sakari Ailus
2022-09-22 12:51 ` Geert Uytterhoeven
2022-09-22 13:27 ` Lad, Prabhakar
2022-09-22 13:51 ` Laurent Pinchart
2022-09-22 19:13 ` Geert Uytterhoeven
2022-09-22 13:12 ` Lad, Prabhakar
2022-09-21 21:35 ` Sakari Ailus
2022-09-22 12:53 ` Lad, Prabhakar
2022-09-22 13:02 ` Sakari Ailus
2022-09-22 13:16 ` Lad, Prabhakar
2022-09-05 23:04 ` [PATCH v2 4/4] media: platform: Add Renesas RZ/G2L CRU driver Lad Prabhakar
2022-09-22 15:28 ` Laurent Pinchart
2022-09-23 19:02 ` Lad, Prabhakar
2022-09-26 8:59 ` Laurent Pinchart
2022-09-26 16:24 ` Lad, Prabhakar
2022-09-26 16:29 ` Laurent Pinchart
2022-09-26 17:27 ` Lad, Prabhakar
2022-09-26 18:11 ` Laurent Pinchart
2022-09-27 19:23 ` Lad, Prabhakar
2022-09-23 20:14 ` Sakari Ailus
2022-09-24 11:38 ` Lad, Prabhakar
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