[PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support

Hal Feng
2022-09-29T15:51:39Z

From: Emil Renner Berthing <kernel@esmil.dk>

This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com>
---
arch/riscv/Kconfig.socs | 1 +
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
drivers/soc/sifive/sifive_l2_cache.c | 7 +++++++
4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..10f68a4359f9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,7 @@ config SOC_STARFIVE
bool "StarFive SoCs"
select PINCTRL
select RESET_CONTROLLER
+ select SIFIVE_L2
select SIFIVE_PLIC
help
This enables support for StarFive SoC platform hardware.
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
-obj-$(CONFIG_SOC_SIFIVE) += sifive/
+obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..776b30723c04 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0

-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE

config SIFIVE_L2
bool "Sifive L2 Cache controller"
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 010d612f7420..d6637254977f 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -10,6 +10,7 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <asm/cacheinfo.h>
#include <soc/sifive/sifive_l2_cache.h>

@@ -189,6 +190,7 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ unsigned long quirks = (uintptr_t)device_get_match_data(dev);
int nirqs;
int ret;
int i;
@@ -206,6 +208,9 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
if (g_irq[i] < 0)
return g_irq[i];

+ if (quirks & BIT(i))
+ continue;
+
ret = devm_request_irq(dev, g_irq[i], l2_int_handler, 0, pdev->name, NULL);
if (ret)
return dev_err_probe(dev, ret, "Could not request IRQ %d\n", g_irq[i]);
@@ -225,6 +230,8 @@ static int __init sifive_l2_probe(struct platform_device *pdev)
static const struct of_device_id sifive_l2_match[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
+ { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
+ { .compatible = "starfive,jh7110-ccache" },
{ /* sentinel */ }
};

--
2.17.1