From: "Gautham R. Shenoy" <gautham.shenoy@amd.com>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: Perry Yuan <perry.yuan@amd.com>,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Subject: Re: [PATCH 04/15] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros
Date: Fri, 6 Dec 2024 11:51:03 +0530 [thread overview]
Message-ID: <Z1KXz3N1bIfI1pmd@BLRRASHENOY1.amd.com> (raw)
In-Reply-To: <20241205222847.7889-5-mario.limonciello@amd.com>
On Thu, Dec 05, 2024 at 04:28:36PM -0600, Mario Limonciello wrote:
> The FIELD_PREP and FIELD_GET macros improve readability and help
> to avoid shifting bugs.
Indeed.
The code looks better with this.
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
--
Thanks and Regards
gautham.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 45 ++++++++++++++++--------------------
> 1 file changed, 20 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 22e212ca514c5..dbe014f3c2beb 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -22,6 +22,7 @@
>
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> +#include <linux/bitfield.h>
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/init.h>
> @@ -88,6 +89,11 @@ static bool cppc_enabled;
> static bool amd_pstate_prefcore = true;
> static struct quirk_entry *quirks;
>
> +#define AMD_PSTATE_MAX_PERF_MASK GENMASK(7, 0)
> +#define AMD_PSTATE_MIN_PERF_MASK GENMASK(15, 8)
> +#define AMD_PSTATE_DES_PERF_MASK GENMASK(23, 16)
> +#define AMD_PSTATE_EPP_PERF_MASK GENMASK(31, 24)
> +
> /*
> * AMD Energy Preference Performance (EPP)
> * The EPP is used in the CCLK DPM controller to drive
> @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock);
>
> static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
> {
> - u64 epp;
> int ret;
>
> if (!cppc_req_cached) {
> @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
> return ret;
> }
> }
> - epp = (cppc_req_cached >> 24) & 0xFF;
>
> - return (s16)epp;
> + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached);
> }
>
> DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp);
> @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
>
> static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp)
> {
> - int ret;
> -
> u64 value = READ_ONCE(cpudata->cppc_req_cached);
> + int ret;
>
> - value &= ~GENMASK_ULL(31, 24);
> - value |= (u64)epp << 24;
> + value &= ~AMD_PSTATE_EPP_PERF_MASK;
> + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp);
> WRITE_ONCE(cpudata->cppc_req_cached, value);
>
> ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> @@ -533,18 +536,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
> des_perf = 0;
> }
>
> - value &= ~AMD_CPPC_MIN_PERF(~0L);
> - value |= AMD_CPPC_MIN_PERF(min_perf);
> -
> - value &= ~AMD_CPPC_DES_PERF(~0L);
> - value |= AMD_CPPC_DES_PERF(des_perf);
> -
> /* limit the max perf when core performance boost feature is disabled */
> if (!cpudata->boost_supported)
> max_perf = min_t(unsigned long, nominal_perf, max_perf);
>
> - value &= ~AMD_CPPC_MAX_PERF(~0L);
> - value |= AMD_CPPC_MAX_PERF(max_perf);
> + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK |
> + AMD_PSTATE_DES_PERF_MASK);
> + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf);
> + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf);
> + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf);
>
> if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
> trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
> @@ -1571,16 +1571,11 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
> if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
> min_perf = min(cpudata->nominal_perf, max_perf);
>
> - /* Initial min/max values for CPPC Performance Controls Register */
> - value &= ~AMD_CPPC_MIN_PERF(~0L);
> - value |= AMD_CPPC_MIN_PERF(min_perf);
> -
> - value &= ~AMD_CPPC_MAX_PERF(~0L);
> - value |= AMD_CPPC_MAX_PERF(max_perf);
> -
> - /* CPPC EPP feature require to set zero to the desire perf bit */
> - value &= ~AMD_CPPC_DES_PERF(~0L);
> - value |= AMD_CPPC_DES_PERF(0);
> + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK |
> + AMD_PSTATE_DES_PERF_MASK);
> + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf);
> + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0);
> + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf);
>
> /* Get BIOS pre-defined epp value */
> epp = amd_pstate_get_epp(cpudata, value);
> --
> 2.43.0
>
next prev parent reply other threads:[~2024-12-06 6:21 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-05 22:28 [PATCH 00/15] amd-pstate 6.14 cleanups and improvements Mario Limonciello
2024-12-05 22:28 ` [PATCH 01/15] cpufreq/amd-pstate: Add trace event for EPP perf updates Mario Limonciello
2024-12-06 5:05 ` Yuan, Perry
2024-12-06 5:44 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 02/15] cpufreq/amd-pstate: convert mutex use to guard() Mario Limonciello
2024-12-06 6:15 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 03/15] cpufreq/amd-pstate: Drop cached epp_policy variable Mario Limonciello
2024-12-06 6:16 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 04/15] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Mario Limonciello
2024-12-06 6:21 ` Gautham R. Shenoy [this message]
2024-12-05 22:28 ` [PATCH 05/15] cpufreq/amd-pstate: Store the boost numerator as highest perf again Mario Limonciello
2024-12-06 6:25 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 06/15] cpufreq/amd-pstate: Use boost numerator for upper bound of frequencies Mario Limonciello
2024-12-06 6:27 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 07/15] cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success Mario Limonciello
2024-12-06 6:32 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 08/15] cpufreq/amd-pstate: store all values in cpudata struct in khz Mario Limonciello
2024-12-06 6:43 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 09/15] cpufreq/amd-pstate: Change amd_pstate_update_perf() to return an int Mario Limonciello
2024-12-06 6:43 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 10/15] cpufreq/amd-pstate: Move limit updating code Mario Limonciello
2024-12-06 3:10 ` kernel test robot
2024-12-06 15:19 ` Gautham R. Shenoy
2024-12-05 22:28 ` [PATCH 11/15] cpufreq/amd-pstate: Cache EPP value and use that everywhere Mario Limonciello
2024-12-06 16:14 ` Gautham R. Shenoy
2024-12-06 16:16 ` Mario Limonciello
2024-12-05 22:28 ` [PATCH 12/15] cpufreq/amd-pstate: Always write EPP value when updating perf Mario Limonciello
2024-12-05 22:28 ` [PATCH 13/15] cpufreq/amd-pstate: Check if CPPC request has changed before writing to the MSR or shared memory Mario Limonciello
2024-12-05 22:28 ` [PATCH 14/15] cpufreq/amd-pstate: Drop ret variable from amd_pstate_set_energy_pref_index() Mario Limonciello
2024-12-05 22:28 ` [PATCH 15/15] cpufreq/amd-pstate: Set different default EPP policy for Epyc and Ryzen Mario Limonciello
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